ZHCSFY1F December 2016 – April 2024 TDP158
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics, Power Supply
- 5.6 Electrical Characteristics, Differential Input
- 5.7 Electrical Characteristics, TMDS Differential Output
- 5.8 Electrical Characteristics, DDC, I2C, HPD, and ARC
- 5.9 Electrical Characteristics, TMDS Differential Output in DP-Mode
- 5.10 Switching Characteristics, TMDS
- 5.11 Switching Characteristics, HPD
- 5.12 Switching Characteristics, DDC and I2C
- 5.13 Typical Characteristics
- 6 Parameter Measurement Information
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5
Register Maps
- 7.5.1 Local I2C Control BIT Access TAG Convention
- 7.5.2 BIT Access Tag Conventions
- 7.5.3 CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)
- 7.5.4 CSR Bit Field Definitions, REV_ID (address = 08h )
- 7.5.5 CSR Bit Field Definitions – MISC CONTROL 09h (address = 09h)
- 7.5.6 CSR Bit Field Definitions – MISC CONTROL 0Ah (address = 0Ah)
- 7.5.7 CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)
- 7.5.8 CSR Bit Field Definitions – MISC CONTROL 0Ch (address = 0Ch)
- 7.5.9 CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)
- 7.5.10 CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)
- 7.5.11 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
- 7.5.12 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)
- 7.5.13 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)
- 7.5.14 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)
- 7.5.15 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)
- 7.5.16 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)
- 7.5.17 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)
- 7.5.18 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)
- 7.5.19 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
8.2.5 9.1.2 Source Side HDMI /DP Application Using DP-Mode
The TDP158 has a special mode that will allow the device to support either HDMI or DP applications. The device is put into this mode by setting reg09h[5] to 1. The device will self-configure with the following settings and become I2C programmable only. The TDP158 does not support automatic Link Training for DisplayPort. AUX channel bypasses device.
- All four lanes are turned on and configured for 5.4Gbps data rate.
- Sets VOD swing to ≅ 410mV (This value is based upon a VSADJ value of 6kΩ).
- Reg0Ch[7:5] is used to control VOD swing for all lanes.
- Reg0Ch[1:0] is used to control pre-emphasis for all lanes.
- Reg30h[7:2] is used to turn on or off individual lanes as well as informing the TDP158 what the data rate is. This is used for the delay component for pre-emphasis signal.
Figure 8-6 TDP158 in
Dual Role Source Side Application