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ZHCSFZ0D December 2016 – December 2023 DAC38RF80 , DAC38RF83 , DAC38RF84 , DAC38RF85 , DAC38RF90 , DAC38RF93

PRODUCTION DATA

7.3.3 SerDes PLL

The DAC38RFxx has two integrated PLLs, one PLL is to provide the clocking of DAC; the other PLL is to provide the clocking for the high speed SerDes. The reference frequency of the SerDes PLL can be in the range of 100-800 MHz nominal, and 300-800 MHz optimal. The reference frequency is derived from DACCLK divided down by the value in field SerDes_REFCLK_DIV in register SRDS_CLK_CFG (8.5.84), as shown in Figure 7-8. Field SerDes_CLK_SEL in register SRDS_CLK_CFG (8.5.84) determines if the DACCLK input or DAC PLL output is used as the source of the SerDes PLL reference. If the DACCLK input is used, a pre-divider set by field SerDes_REFCLK_PREDIV in register SRDS_CLK_CFG (8.5.84) should be used to reduce the frequency of the DACCLK.

Figure 7-8 Reference Clock of SerDes PLL

During normal operation, the clock generated by PLL is 4-25 times the reference frequency, according to the multiply factor selected through the field MPY] in register SRDS_PLL_CFG (8.5.85). To select the appropriate multiply factor and reference clock frequency, it is first necessary to determine the required PLL output clock frequency. The relationship between the PLL output clock frequency and the lane rate is determined by field RATE in register SRDS_CFG2 (8.5.87) is shown in PLL. Having computed the PLL output frequency, the reference frequency can be obtained by dividing this by the multiply factor specified through MPY.

Table 7-3 PLL

RATE	LINE RATE	PLL OUTPUT FREQUENCY
00	x Gbps	0.25x GHz
01	x Gbps	0.5x GHz
10	x Gbps	1x GHz
11	x Gbps	2x GHz

Table 7-4 SerDes PLL Multiplier (MPY) Values

MPY	EFFECT
0x10	4x
0x14	5x
0x18	6x
0x20	8x
0x21	8.25x
0x28	10x
0x30	12x
0x32	12.5x
0x3C	15x
0x40	16x
0x42	16.5x
0x50	20x
0x58	22x
0x64	25x
Other codes	Reserved

The wide range of multiply factors combined with the different rate modes means it is often possible to achieve a given line rate from multiple different reference frequencies. The configuration which utilizes the highest reference frequency achievable is always preferable.

The SerDes PLL VCO must be in the nominal range of 1.5625 - 3.125 GHz. It is necessary to adjust the loop filter depending on the operating frequency of the VCO. If the PLL output frequency is below 2.17 GHz, VRANGE in register SRDS_PLL_CFG (8.5.84) should be set high.

Performance of the integrated PLL can be optimized according to the jitter characteristics of the reference clock by setting the appropriate loop bandwidth through field LB in register SRDS_PLL_CFG (8.5.84). The loop bandwidth is obtained by dividing the reference frequency by BWSCALE, where the BWSCALE is a function of both LB and PLL output frequency as shown in Table 7-5.

Table 7-5 SerDes PLL Loop Bandwidth Selection

LB	EFFECT	BWSCALE vs PLL OUTPUT FREQUENCY
		3.125 GHz	2.17 GHz	1.5625 GHz
00	Medium loop bandwidth	13	14	16
01	Ultra high loop bandwidth	7	8	8
10	Low loop bandwidth	21	23	30
11	High loop bandwidth	10	11	14

An approximate loop bandwidth of 8 – 30 MHz is suitable and recommended for most systems where the reference clock is through low jitter clock input buffer. For systems where the reference clock is through a low jitter input cell, but of low quality, an approximate loop bandwidth of less than 8 MHz may offer better performance. For systems where the reference clock is cleaned through an ultra-low jitter LC-based cleaner PLL, a high loop bandwidth up to 60 MHz is more appropriate. Note that the use of ultra-high loop bandwidth setting is not recommended for PLL multiply factor of less than 8.

A free running clock output is available when field ENDIVCLK in register SRDS_PLL_CFG (8.5.85) is set high. It runs at a fixed divided-by-80 of the PLL output frequency and can be output on the ALARM pin by setting field DTEST to “0001” (lanes 0 – 3) or “0010” (lanes 4 – 7) in register DTEST (8.5.76).