7.9 PLL2 Specification Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended Operating Conditions and are not assured.
| PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
| fdoubler_max |
Doubler input frequency |
EN_PLL2_REF_2X = 1(2);
OSCin duty cycle 40% to 60% |
|
|
125 |
MHz |
| fPD2 |
Phase detector frequency (1) |
|
|
|
250 |
MHz |
| PN10kHz |
PLL 1/f noise at 10-kHz offset.(3) Normalized to
1-GHz output frequency |
400-kHz loop bandwidth |
|
–120 |
|
dBc/Hz |
| fVCO |
VCO tuning range |
|
5870 |
|
6175 |
MHz |
| |ΔTCL| |
Allowable temperature drift for continuous lock(4) |
After programming for lock, no changes to output configuration are permitted to assure continuous lock |
|
|
145 |
°C |
| BWmin |
Minimum PLL2 bandwidth |
|
|
90 |
|
kHz |
| BWmax |
Maximum PLL2 bandwidth |
|
|
1000 |
|
kHz |
(1) Assured by characterization. ATE tested at
258 MHz.
(2) The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.
(3) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10-kHz offset and a 1-GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) – 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f).
(4) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value and still have the part stay in lock; this implies the part will work over the entire frequency range. However, if the temperature drifts more than the maximum allowable drift for continuous lock, it will be necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature must never drift outside the frequency range of –40°C to 105°C without violating specifications.