米6体育平台手机版

ZHCSG17B January 2017 – July 2019 LMK04610

PRODUCTION DATA.

7.12 Jitter and Phase Noise Characteristics for CLKoutX and OSCout

3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < T_A < 85°C and T_PCB ≤ 105°C. Typical values at VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, T_A = 25°C, at the Recommended Operating Conditions and are not assured.

PARAMETER		TEST CONDITIONS		TYP	UNIT
L(f)_{CLKout/OSCout}NF	Noise floor 20-MHz offset ≤ 100-Hz loop bandwidth for PLL1 400-kHz loop bandwidth for PLL2⁽¹⁾	122.88 MHz	HSDS 4 mA	–166	dBc/Hz
			HSDS 6 mA	–166
			HSDS 8 mA	–166
			HCSL 16 mA	–165
			OSCout, HSDS 4 mA	–161
			OSCout, HSDS 8 mA	–161
			OSCout, LVCMOS	–156
L(f)_CLKoutNF,ADLY	Noise floor with analog delay enabled 20-MHz offset ≤ 100-Hz loop bandwidth for PLL1 400-kHz loop bandwidth for PLL2⁽¹⁾	122.88 MHz, maximum analog delay setting	HSDS 4 mA	–151	dBc/Hz
			HSDS 6 mA	–151
			HSDS 8 mA	–151
			HCSL 16 mA	–151
L(f)_CLKoutPN	SSB phase noise⁽³⁾ 122.88-MHz output frequency ≤ 100-Hz loop bandwidth for PLL1 400-kHz loop bandwidth for PLL2 ⁽¹⁾⁽²⁾	Offset = 100 Hz		–97	dBc/Hz
		Offset = 1 kHz		–126
		Offset = 10 kHz		–139
		Offset = 100 kHz		–147
		Offset = 800 kHz		–158
		Offset = 1 MHz		–159
		Offset = 10 MHz	HSDS 8 mA	–166
		Offset = 10 MHz	HCSL 16 mA	–165
L(f)_OSCoutPN	SSB phase noise 122.88-MHz output frequency ≤ 100-Hz loop bandwidth for PLL1 400-kHz loop bandwidth for PLL2 ⁽¹⁾⁽²⁾	Offset = 100 Hz		–97	dBc/Hz
		Offset = 1 kHz		–136
		Offset = 10 kHz		–148
		Offset = 100 kHz		–157
		Offset = 1 MHz	HSDS 4 mA	–160
		Offset = 10 MHz	HSDS 8 mA	–160
J_CLKout	f_CLKout = 122.88 MHz Integrated RMS jitter ≤ 100-Hz loop bandwidth for PLL1 400-kHz loop bandwidth for PLL2 ⁽¹⁾⁽⁴⁾	HSDS 8 mA, BW = 100 Hz to 20 MHz		160	fs rms
		HSDS 8 mA, BW = 10 kHz to 20 MHz		75
		HCSL 16 mA, BW = 100 Hz to 20 MHz		160
		HCSL 16 mA, BW = 10 kHz to 20 MHz		75

(1) VCXO used is a 122.88-MHz Crystek CVHD-950-122.880.

(2) The input is configured to either a full swing AC-coupled, single-ended signal or a LVDS like AC-coupled differential signal. The input frequency is 122.88 MHz. VDD_IN is at 1.8 V.

(3) Phase noise is defined in dual-loop mode and in single PLL mode if OSCin is used as the ref input.

(4) PLL1 and PLL2 settings optimized to meet multicarrier GSM phase-noise specifications. For RMS jitter optimized settings, see PLL1 and PLL2.