7.19 Timing Diagram

Each serial interface access cycle is exactly (2 + N) bytes long, where N is the number of data bytes. A frame is initiated by asserting SCS* low. The frame ends when SCS* is de-asserted high. The first bit transferred is the R/W bit. The next 15 bits are the register address and the remaining bits are data. For all writes, data is committed in bytes as the 8^th data bit of a data field is clocked in on the rising edge of SCL. If the write access is not an even multiple of 8 clocks, the trailing data bits are not committed. On read access, data is clocked out on the falling edge of SCL on the SDO pin.

Four-wire mode read back has the same timing as the SDIO pin.

R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.

See Programming for more details.

Figure 1. SPI Timing Diagram