10.2.1 Design Requirements

Given a remote radio head (RRU) type application which needs to clock some ADCs, DACs, FPGA, SERDES, and an LO. The input clock is a recovered clock which needs jitter cleaning. The FPGA clock should have a clock output on power up. A summary of clock input and output requirements are as follows:

Clock Input:

• 122.88-MHz recovered clock.

Clock Outputs:

• 1x 245.76-MHz clock for ADC
• 2x 983.04-MHz clock for DAC
• 2x 122.88-MHz clock for FPGA
• 1x 122.88-MHz clock for SERDES

It is also desirable to have the holdover feature engage if the recovered clock reference is ever lost. The following information reviews the steps to produce this design.

If JESD204B support is also required for the clock outputs, see JEDEC JESD204B for more details.