9.3.1.1.3 Input Clock Switching – Automatic Mode

When CLKINSEL1_MODE = 0, the input clock switching is in automatic mode. The priority of each input clock can be individually set by programming CLKINx_PRIO[1:0] as shown in Table 4:

SPACER

The clock inputs in this mode are monitored by on-chip LOS detection circuits. The device reads the priority bits at start-up and locks to the input clock with highest priority. In the event of input clock loss, the internal PLL switches to the next available clock. TI recommends using holdover mode while using the automatic reference clock switching. See Holdover for programming the holdover mode.

In this case, the outputs clocks see minimum disturbance while switching from one clock to the other. In the event of reference clock loss, the PLL1 enters the holdover mode. After the internal logic switches the PLL1 input clock to the next available clock as per priority setting, PLL1 holdover exit is initiated and PLL1 relocks to the new clock with minimum disturbance. Figure 16 describes the sequence of operations in the automatic reference clock switching mode while holdover is enabled and programmed.

Figure 16. Input Clock Switching – Priority Loop