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ZHCSG17B January 2017 – July 2019 LMK04610

PRODUCTION DATA.

9.3.5.1.1 PLL1 Proportional Modes

PLL1 bandwidth can be increased or decreased even further by using the different PROP modes (see Table 14).

Table 14. PLL1 Proportional Modes

PROP MODE	REGISTER SETTINGS	DUTY CYCLE OF CLOCK
Default	PLL1_RDIV_4CY = 0 PLL1_NDIV_4CY = 0	50%
Low Pulse mode	PLL1_RDIV_4CY = 1 PLL1_NDIV_4CY = 1 PLL1_FBCLK_INV = 1 CLKINx_PLL1_INV = 1	(4/DIV) * 100
High Pulse mode	PLL1_RDIV_4CY = 1 PLL1_NDIV_4CY = 1 PLL1_FBCLK_INV = 0 CLKINx_PLL1_INV = 0	(1-4/DIV) * 100

In the default input mode, the proportional is effective for 50% of the PFD clock period. Using low pulse mode, the effect of the proportional is reduced which results in a reduced PLL bandwidth. Similarly, using the high pulse mode, the proportional is effective for more than half of the PFD cycle, which results in higher bandwidth.

PLL1_INTG settings affect the integral gain in the loop. TI recommends using setting 0 in normal mode and higher settings only for Fast lock using PLL1_INTG_FL.