9.3.5.3 Digital Lock Detect

Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference path (R) and the feedback path (N) of the PLL. When the time error (phase error) between the two signals is less than a specified window size (ε), a lock detect count increments.

When the PLL1 lock detect count reaches a user specified value, PLL1_LOCKDET_CYC_CNT, lock detect is asserted true. Once digital lock detect is true, a single phase comparison outside the specified window causes the digital lock detect to be asserted false (see Figure 40).

Figure 40. PLL1 Digital Lock Detect Flowchart

PLL2 DLD requires register 0xF6 = 0x02, 0x85 = 0x00, and 0x86 = 0x00 set. Then to program register 0xAD for valid digital lock detect. See Recommended Programming Sequence. When the PLL2 lock detect count reaches a user specified value, PLL2_LOCKDET_CYC_CNT, lock detect is asserted true. Once digital lock detect is true, a single phase comparison outside the specified window causes the digital lock detect to be asserted false (see Figure 41).

Figure 41. PLL2 Digital Lock Detect Flowchart

This incremental lock detect count feature functions as a digital filter to ensure that lock detect isn't asserted for only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial phase lock.

The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.

Figure 42. Digital Lock Detect Implementation