ZHCSGA6A February   2017  – June 2017 ADS114S06 , ADS114S08

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      功能方框图
  4. 4 修订历史记录
  5. 5 Device Family Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Multiplexer
      2. 9.3.2  Low-Noise Programmable Gain Amplifier
        1. 9.3.2.1 PGA Input-Voltage Requirements
        2. 9.3.2.2 PGA Rail Flags
        3. 9.3.2.3 Bypassing the PGA
      3. 9.3.3  Voltage Reference
        1. 9.3.3.1 Internal Reference
        2. 9.3.3.2 External Reference
        3. 9.3.3.3 Reference Buffers
      4. 9.3.4  Clock Source
      5. 9.3.5  Delta-Sigma Modulator
      6. 9.3.6  Digital Filter
        1. 9.3.6.1 Low-Latency Filter
          1. 9.3.6.1.1 Low-Latency Filter Frequency Response
          2. 9.3.6.1.2 Data Conversion Time for the Low-Latency Filter
        2. 9.3.6.2 Sinc3 Filter
          1. 9.3.6.2.1 Sinc3 Filter Frequency Response
          2. 9.3.6.2.2 Data Conversion Time for the Sinc3 Filter
        3. 9.3.6.3 Note on Conversion Time
        4. 9.3.6.4 50-Hz and 60-Hz Line Cycle Rejection
        5. 9.3.6.5 Global Chop Mode
      7. 9.3.7  Excitation Current Sources (IDACs)
      8. 9.3.8  Bias Voltage Generation
      9. 9.3.9  System Monitor
        1. 9.3.9.1 Internal Temperature Sensor
        2. 9.3.9.2 Power Supply Monitors
        3. 9.3.9.3 Burn-Out Current Sources
      10. 9.3.10 Status Register
        1. 9.3.10.1 POR Flag
        2. 9.3.10.2 RDY Flag
        3. 9.3.10.3 PGA Output Voltage Rail Monitors
        4. 9.3.10.4 Reference Monitor
      11. 9.3.11 General-Purpose Inputs and Outputs (GPIOs)
      12. 9.3.12 Low-Side Power Switch
      13. 9.3.13 Cyclic Redundancy Check (CRC)
      14. 9.3.14 Calibration
        1. 9.3.14.1 Offset Calibration
        2. 9.3.14.2 Gain Calibration
    4. 9.4 Device Functional Modes
      1. 9.4.1 Reset
        1. 9.4.1.1 Power-On Reset
        2. 9.4.1.2 RESET Pin
        3. 9.4.1.3 Reset by Command
      2. 9.4.2 Power-Down Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Conversion Modes
        1. 9.4.4.1 Continuous Conversion Mode
        2. 9.4.4.2 Single-Shot Conversion Mode
        3. 9.4.4.3 Programmable Conversion Delay
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Serial Data Input (DIN)
        4. 9.5.1.4 Serial Data Output and Data Ready (DOUT/DRDY)
        5. 9.5.1.5 Data Ready (DRDY)
        6. 9.5.1.6 Timeout
      2. 9.5.2 Data Format
      3. 9.5.3 Commands
        1. 9.5.3.1  NOP
        2. 9.5.3.2  WAKEUP
        3. 9.5.3.3  POWERDOWN
        4. 9.5.3.4  RESET
        5. 9.5.3.5  START
        6. 9.5.3.6  STOP
        7. 9.5.3.7  SYOCAL
        8. 9.5.3.8  SYGCAL
        9. 9.5.3.9  SFOCAL
        10. 9.5.3.10 RDATA
        11. 9.5.3.11 RREG
        12. 9.5.3.12 WREG
      4. 9.5.4 Reading Data
        1. 9.5.4.1 Read Data Direct
        2. 9.5.4.2 Read Data by RDATA Command
        3. 9.5.4.3 Sending Commands When Reading Data
      5. 9.5.5 Interfacing with Multiple Devices
    6. 9.6 Register Map
      1. 9.6.1 Configuration Registers
        1. 9.6.1.1  Device ID Register (address = 00h) [reset = xxh]
          1. Table 26. Device ID (ID) Register Field Descriptions
        2. 9.6.1.2  Device Status Register (address = 01h) [reset = 80h]
          1. Table 27. Device Status (STATUS) Register Field Descriptions
        3. 9.6.1.3  Input Multiplexer Register (address = 02h) [reset = 01h]
          1. Table 28. Input Multiplexer (INPMUX) Register Field Descriptions
        4. 9.6.1.4  Gain Setting Register (address = 03h) [reset = 00h]
          1. Table 29. Gain Setting (PGA) Register Field Descriptions
        5. 9.6.1.5  Data Rate Register (address = 04h) [reset = 14h]
          1. Table 30. Data Rate (DATARATE) Register Field Descriptions
        6. 9.6.1.6  Reference Control Register (address = 05h) [reset = 10h]
          1. Table 31. Reference Control (REF) Register Field Descriptions
        7. 9.6.1.7  Excitation Current Register 1 (address = 06h) [reset = 00h]
          1. Table 32. Excitation Current Register 1 (IDACMAG) Register Field Descriptions
        8. 9.6.1.8  Excitation Current Register 2 (address = 07h) [reset = FFh]
          1. Table 33. Excitation Current Register 2 (IDACMUX) Register Field Descriptions
        9. 9.6.1.9  Sensor Biasing Register (address = 08h) [reset = 00h]
          1. Table 34. Sensor Biasing (VBIAS) Register Field Descriptions
        10. 9.6.1.10 System Control Register (address = 09h) [reset = 10h]
          1. Table 35. System Control (SYS) Register Field Descriptions
        11. 9.6.1.11 Reserved Register (address = 0Ah) [reset = 00h]
          1. Table 36. Reserved Register Field Descriptions
        12. 9.6.1.12 Offset Calibration Register 1 (address = 0Bh) [reset = 00h]
          1. Table 37. Offset Calibration Register 1 (OFCAL0) Register Field Descriptions
        13. 9.6.1.13 Offset Calibration Register 2 (address = 0Ch) [reset = 00h]
          1. Table 38. Offset Calibration Register 2 (OFCAL1) Register Field Descriptions
        14. 9.6.1.14 Reserved Register (address = 0Dh) [reset = 00h]
          1. Table 39. Reserved Register Field Descriptions
        15. 9.6.1.15 Gain Calibration Register 1 (address = 0Eh) [reset = 00h]
          1. Table 40. Gain Calibration Register 1 (FSCAL0) Field Descriptions
        16. 9.6.1.16 Gain Calibration Register 2 (address = 0Fh) [reset = 40h]
          1. Table 41. Gain Calibration Register 2 (FSCAL1) Field Descriptions
        17. 9.6.1.17 GPIO Data Register (address = 10h) [reset = 00h]
          1. Table 42. GPIO Data (GPIODAT) Register Field Descriptions
        18. 9.6.1.18 GPIO Configuration Register (address = 11h) [reset = 00h]
          1. Table 43. GPIO Configuration (GPIOCON) Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Serial Interface Connections
      2. 10.1.2 Analog Input Filtering
      3. 10.1.3 External Reference and Ratiometric Measurements
      4. 10.1.4 Establishing a Proper Input Voltage
      5. 10.1.5 Unused Inputs and Outputs
      6. 10.1.6 Pseudo Code Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Register Settings
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
    2. 11.2 Power-Supply Sequencing
    3. 11.3 Power-On Reset
    4. 11.4 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 开发支持
    2. 13.2 文档支持
      1. 13.2.1 相关文档
    3. 13.3 相关链接
    4. 13.4 接收文档更新通知
    5. 13.5 社区资源
    6. 13.6 商标
    7. 13.7 静电放电警告
    8. 13.8 Glossary
  14. 14机械、封装和可订购信息

7.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –50°C to +125°C; Typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal oscillator, all data rates, and global chop disabled (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Absolute input current PGA bypassed,
AVSS + 0.1 V ≤ V(AINx) ≤ AVDD – 0.1 V		 0.5 nA
PGA enabled, all gains,
V(AINx)MIN ≤ V(AINx) ≤ V(AINx)MAX 		–2 0.1 2
Absolute input current drift PGA bypassed,
AVSS + 0.1 V ≤ V(AINx) ≤ AVDD – 0.1 V		 2 pA/°C
PGA enabled, all gains,
V(AINx)MIN ≤ V(AINx) ≤ V(AINx)MAX 		2
Differential input current PGA bypassed,
VCM = AVDD / 2, –VREF ≤ VIN ≤ VREF 		1 nA/V
PGA enabled, all gains,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain		 –1 0.02 1 nA
Differential input current drift PGA bypassed,
VCM = AVDD / 2, –VREF ≤ VIN ≤ VREF 		3 pA/°C
PGA enabled, all gains,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain		 1
PGA
Gain settings 1, 2, 4, 8, 16,
32, 64, 128
Startup time Enabling the PGA in conversion mode 190 µs
SYSTEM PERFORMANCE
Resolution (no missing codes) 16 Bits
DR Data rate 2.5, 5, 10, 16.6,
20, 50, 60, 100,
200, 400, 800,
1000, 2000, 4000		 SPS
INL Integral nonlinearity (best fit) PGA bypassed, VCM = AVDD / 2 1 10 ppmFSR
PGA enabled, gain = 1 to 8, VCM = AVDD / 2 2 15
PGA enabled, gain = 16 to 128, VCM = AVDD / 2,
TA = –40°C to +85°C		 3 15
VIO Input offset voltage TA = 25°C, PGA bypassed –120 20 120 µV
TA = 25°C, PGA enabled, gain = 1 to 8 –120 / Gain 20 / Gain 120 / Gain
TA = 25°C, PGA enabled, gain = 16 to 128 –15 2 15
TA = 25°C, PGA bypassed, after internal offset calibration On the order of noisePP at the set DR and gain
TA = 25°C, PGA enabled, gain = 1 to 128, after internal offset calibration On the order of noisePP at the set DR and gain
TA = 25°C, PGA bypassed, global chop enabled –2 0.2 2
TA = 25°C, PGA enabled, gain = 1 to 128,
global chop enabled 		–2 0.2 2
Offset drift TA = –40°C to +85°C, PGA bypassed –75 10 75 nV/°C
TA = –40°C to +85°C, PGA enabled, gain = 1 to 128 –100 15 100
PGA bypassed –75 10 75
PGA enabled, gain = 1 to 8 –200 15 200
PGA enabled, gain = 16 to 128 –150 15 150
PGA bypassed, global chop enabled –10 2 10
PGA enabled, gain = 1 to 128, global chop enabled –10 2 10
SYSTEM PERFORMANCE (continued)
Gain error(1) TA = 25°C, PGA bypassed 40 120 ppm
TA = 25°C, PGA enabled, gain = 1 to 32   40 120
TA = 25°C, PGA enabled, gain = 64 and 128 40 200
Gain drift(1) TA = –40°C to +85°C, PGA bypassed 0.5 1 ppm/°C
TA = –40°C to +85°C, PGA enabled, gain = 1 to 128 0.5 2
PGA bypassed 0.5 1
PGA enabled, gain = 1 to 128 1 4
Noise (input-referred) See the Noise Performance section
NMRR Normal-mode rejection ratio(2) fIN = 50 Hz or 60 Hz (±1 Hz), DR = 10 SPS,
sinc3 filter		 88 dB
fIN = 50 Hz or 60 Hz (±1 Hz), DR = 10 SPS,
sinc3 filter, external fCLK = 4.096 MHz		 102
fIN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS,
low-latency filter		 79
fIN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS,
low-latency filter, external fCLK = 4.096 MHz		 95
fIN = 50 Hz (±1 Hz), DR = 50 SPS, sinc3 filter 87
fIN = 50 Hz (±1 Hz), DR = 50 SPS,
sinc3 filter, external fCLK = 4.096 MHz		 101
fIN = 60 Hz (±1 Hz), DR = 60 SPS, sinc3 filter 89
fIN = 60 Hz (±1 Hz), DR = 60 SPS,
sinc3 filter, external fCLK = 4.096 MHz		 105
CMRR Common-mode rejection ratio At dc 110 120 dB
fCM = 50 Hz or 60 Hz (±1 Hz),
DR = 2.5 SPS to 10 SPS, sinc3 filter		 120 130
fCM = 50 Hz or 60 Hz (±1 Hz),
DR = 2.5 SPS, 5 SPS, 10 SPS, 20 SPS, low-latency filter		 115 125
PSRR Power-supply rejection ratio AVDD at dc 90 105 dB
AVDD at 50 Hz or 60 Hz 100 115
DVDD at dc 100 115
VOLTAGE REFERENCE INPUTS
Absolute input current Reference buffers disabled, external VREF = 2.5 V,
REFP1/REFN1 inputs		 -6 4 6 µA/V
Reference buffers enabled, external VREF = 2.5 V,
REFP1/REFN1 inputs		 –15 5 15 nA
INTERNAL VOLTAGE REFERENCE
VREF Output voltage 2.5 V
Accuracy TA = 25°C, TQFP package –0.05% ±0.01% 0.05%
TA = 25°C, VQFN package –0.1% ±0.01% 0.1%
Temperature drift TA = –40°C to +85°C 2.5 8 ppm/°C
TA = –50°C to +125°C 3 10
Output current AVDD = 2.7 V to 3.3 V, sink and source –5 5 mA
AVDD = 3.3 V to 5.25 V, sink and source –10 10
Short-circuit current limit Sink and source 70 100 mA
PSRR Power-supply rejection ratio AVDD at dc 85 dB
Load regulation AVDD = 2.7 V to 3.3 V,
load current = –5 mA to 5 mA		 8 µV/mA
AVDD = 3.3 V to 5.25 V,
load current = –10 mA to 10 mA		 8
Startup time 1-µF capacitor on REFOUT, 0.001% settling 5.9 ms
Capacitive load stability Capacitor on REFOUT 1 47 µF
Reference noise f = 0.1 Hz to 10 Hz, 1-µF capacitor on REFOUT 9 µVPP
INTERNAL OSCILLATOR
fCLK Frequency 4.096 MHz
Accuracy –1.5% 1.5%
EXCITATION CURRENT SOURCES (IDACS)
Current settings 10, 50, 100,
250, 500, 750,
1000, 1500, 2000		 µA
Compliance voltage(3) 10 µA to 750 µA, 0.1% deviation AVSS AVDD – 0.4 V
1 mA to 2 mA, 0.1% deviation AVSS AVDD – 0.6
Accuracy (each IDAC) TA = 25°C, 10 µA to 100 µA –5% ±0.7% 5%
TA = 25°C, 250 µA to 2 mA –3% ±0.5% 3%
Current mismatch between IDACs TA = 25°C, 10 µA to 100 µA 0.15% 0.8%
TA = 25°C, 250 µA to 750 µA 0.10% 0.6%
TA = 25°C, 1 mA to 2 mA 0.07% 0.4%
Temperature drift (each IDAC) 10 µA to 750 µA 20 120 ppm/°C
1 mA to 2 mA 10 80
Temperature drift matching between IDACs 10 µA to 100 µA 3 25 ppm/°C
250 µA to 2 mA 2 15
Startup time With internal reference already settled. From end of WREG command to current flowing out of pin. 22 µs
BIAS VOLTAGE
VBIAS Output voltage settings (AVDD + AVSS) / 2,
(AVDD + AVSS) / 12		 V
Output impedance 350 Ω
Startup time Combined capacitive load on all selected analog inputs CLOAD = 1 µF, 0.1% settling 2.8 ms
BURNOUT CURRENT SOURCES (BOCS)
Current settings 0.2, 1, 10 µA
Accuracy 0.2 µA, sinking or sourcing ±8%
1 µA, sinking or sourcing ±4%
10 µA, sinking or sourcing ±2%
PGA RAIL DETECTION
Positive rail threshold Referred to the output of the PGA AVDD – 0.15 V
Negative rail threshold Referred to the output of the PGA AVSS + 0.15 V
REFERENCE DETECTION
Threshold 1 0.3 V
Threshold 2 1/3·(AVDD – AVSS) V
Threshold 2 accuracy –3% ±1% 3%
Pull-together resistance 10 MΩ
SUPPLY VOLTAGE MONITORS
Accuracy (AVDD – AVSS) / 4 monitor ±1%
DVDD / 4 monitor ±1%
TEMPERATURE SENSOR
Output voltage TA = 25°C 129 mV
Temperature coefficient 403 µV/°C
LOW-SIDE POWER SWITCH
RON On-resistance 1 3 Ω
Current through switch 75 mA
GENERAL-PURPOSE INPUT/OUTPUTS (GPIOs)
VIL Logic input level, low AVSS – 0.05 0.3 AVDD V
VIH Logic input level, high 0.7 AVDD AVDD + 0.05 V
VOL Logic output level, low IOL = 1 mA AVSS 0.2 AVDD V
VOH Logic output level, high IOH = 1 mA 0.8 AVDD AVDD V
DIGITAL INPUT/OUTPUTS
VIL Logic input level, low DGND 0.3 IOVDD V
VIH Logic input level, high 0.7 IOVDD IOVDD V
VOL Logic output level, low IOL = 1 mA DGND 0.2 IOVDD V
VOH Logic output level, high IOH = 1 mA 0.8 IOVDD IOVDD V
Input current DGND ≤ VDigital Input ≤ IOVDD –1 1 µA
ANALOG SUPPLY CURRENT (AVDD = 3.3 V, External Reference, Internal Reference Disabled, Reference Buffers Disabled, IDACs Disabled, VBIAS Disabled, Flags Disabled, Internal Oscillator, All Data Rates, VIN = 0 V)
IAVDD Analog supply current Power-down mode 0.1 1.5 µA
Standby mode, PGA bypassed 70
Conversion mode, PGA bypassed 85
Conversion mode, PGA enabled, gain = 1, 2 120 135
Conversion mode, PGA enabled, gain = 4, 8 140 155
Conversion mode, PGA enabled, gain = 16, 32 165 180
Conversion mode, PGA enabled, gain = 64 200
Conversion mode, PGA enabled, gain = 128 250
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 3.3 V)
IAVDD Analog supply current Internal 2.5-V reference, no external load 185 280 µA
Positive reference buffer 35 60
Negative reference buffer 25 40
VBIAS buffer, no external load 10
IDAC overhead, 10 µA to 250 µA 20 35
IDAC overhead, 500 µA to 750 µA 30
IDAC overhead, 1 mA 40
IDAC overhead, 1.5 mA 50
IDAC overhead, 2 mA 65
PGA rail detection and reference detection circuit 10
DIGITAL SUPPLY CURRENT (DVDD = IOVDD = 3.3 V, All Data Rates, SPI Not Active)
IDVDD + IIOVDD Digital supply current Power-down mode, internal oscillator 0.1 µA
Standby mode, internal oscillator 185
Conversion mode, internal oscillator 225 300
Conversion mode, external fCLK = 4.096 MHz 195
POWER DISSIPATION (AVDD = DVDD = IOVDD = 3.3 V, Internal Reference Enabled, Reference Buffers Disabled, IDACs Disabled, VBIAS Disabled, Flags Disabled, Internal Oscillator, All Data Rates, VIN = 0 V, SPI Not Active)
PD Power dissipation Conversion mode, PGA enabled, gain = 1 1.75 mW
(1) Excluding error of voltage reference.
(2) See the 50-Hz and 60-Hz Line Cycle Rejection section for more information.
(3) The IDAC current does not change by more than 0.1% from the nominal value when staying within the specified compliance voltage.
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