The ADC12D1620 has a differential clock input, CLK+ and CLK–, which must be driven with an AC-coupled, differential clock signal. This provides the level shifting necessary so that the clock can be driven with LVDS, PECL, LVPECL, or CML levels. The clock inputs are internally terminated to 100-Ω differential and self-biased. This section covers coupling, frequency range, level, duty-cycle, jitter, and layout considerations.