Although the ADC12D1620 device is tested and its performance is specified with a differential 1.6-GHz sampling clock, it typically functions well over the input clock-frequency range; see f_{CLK (min)} and f_{CLK (max)} in Converter Electrical Characteristics: AC Electrical Characteristics. Operation up to f_{CLK (max)} is possible if the maximum ambient temperatures indicated are not exceeded. Operating at sample rates above f_{CLK (max)} for the maximum ambient temperature may result in reduced device reliability and product lifetime. This is due to the fact that higher sample rates results in higher power consumption and die temperatures. If in non-LSPSM and f_CLK < 300 MHz, enable LFS in the Control Register (Addr: 0h; Bit: 8). In LSPSM, the LFS bit is already enabled.