The performance of the ADC12D1620 in DES mode depends on how well the two channels are interleaved (that is, that the clock samples either channel with precisely a 50% duty-cycle); each channel has the same offset (nominally code 2047/2048), and each channel has the same full-scale range. The ADC12D1620 device includes an automatic clock phase background adjustment in DES mode to automatically and continuously adjust the clock phase of the I and Q channels. In addition to this, the residual fixed timing skew offset may be further manually adjusted, and further reduce timing spurs for specific applications. See DES Timing Adjust (Addr: 7h). As the DES timing adjust is programmed from 0d to 127d, the magnitude of the Fs/2-Fin timing interleaving spur decreases to a local minimum and then increases again. The default, nominal setting of 64d may or may not coincide with this local minimum. The user may manually skew the global timing to achieve the lowest possible timing interleaving spur.