During calibration, the digital outputs (including DI, DId, DQ, DQd and OR) are set logic-low, to reduce noise. The DCLK runs continuously during calibration. After the calibration is completed and the CalRun signal is logic-low, it takes an additional 60 sampling clock cycles before the output of the ADC12D1620 is valid converted data from the analog inputs. This is the time it takes for the pipeline to flush, as well as for other internal processes.