ZHCSGL4C June   2017  – April 2019 LMX2595

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  Reference Path
        1. 7.3.2.1 OSCin Doubler (OSC_2X)
        2. 7.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3 Programmable Multiplier (MULT)
        4. 7.3.2.4 Post-R Divider (PLL_R)
        5. 7.3.2.5 State Machine Clock
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N-Divider and Fractional Circuitry
      5. 7.3.5  MUXout Pin
        1. 7.3.5.1 Lock Detect
        2. 7.3.5.2 Readback
      6. 7.3.6  VCO (Voltage-Controlled Oscillator)
        1. 7.3.6.1 VCO Calibration
        2. 7.3.6.2 Determining the VCO Gain
      7. 7.3.7  Channel Divider
      8. 7.3.8  VCO Doubler
      9. 7.3.9  Output Buffer
      10. 7.3.10 Power-Down Modes
      11. 7.3.11 Phase Synchronization
        1. 7.3.11.1 General Concept
        2. 7.3.11.2 Categories of Applications for SYNC
        3. 7.3.11.3 Procedure for Using SYNC
        4. 7.3.11.4 SYNC Input Pin
      12. 7.3.12 Phase Adjust
      13. 7.3.13 Fine Adjustments for Phase Adjust and Phase SYNC
      14. 7.3.14 Ramping Function
        1. 7.3.14.1 Manual Pin Ramping
          1. 7.3.14.1.1 Manual Pin Ramping Example
        2. 7.3.14.2 Automatic Ramping
          1. 7.3.14.2.1 Automatic Ramping Example (Triangle Wave)
      15. 7.3.15 SYSREF
        1. 7.3.15.1 Programmable Fields
        2. 7.3.15.2 Input and Output Pin Formats
          1. 7.3.15.2.1 Input Format for SYNC and SysRefReq Pins
          2. 7.3.15.2.2 SYSREF Output Format
        3. 7.3.15.3 Examples
        4. 7.3.15.4 SYSREF Procedure
      16. 7.3.16 SysRefReq Pin
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power-Up Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
      3. 7.5.3 General Programming Requirements
    6. 7.6 Register Maps
      1. 7.6.1  General Registers R0, R1, & R7
        1. Table 25. Field Descriptions
      2. 7.6.2  Input Path Registers
        1. Table 26. Field Descriptions
      3. 7.6.3  Charge Pump Registers (R13, R14)
        1. Table 27. Field Descriptions
      4. 7.6.4  VCO Calibration Registers
        1. Table 28. Field Descriptions
      5. 7.6.5  N Divider, MASH, and Output Registers
        1. Table 29. Field Descriptions
      6. 7.6.6  SYNC and SysRefReq Input Pin Register
        1. Table 30. Field Descriptions
      7. 7.6.7  Lock Detect Registers
        1. Table 31. Field Descriptions
      8. 7.6.8  MASH_RESET
        1. Table 32. Field Descriptions
      9. 7.6.9  SysREF Registers
        1. Table 33. Field Descriptions
      10. 7.6.10 CHANNEL Divider And VCO Doubler Registers
        1. Table 34. Field Descriptions
      11. 7.6.11 Ramping and Calibration Fields
        1. Table 35. Field Descriptions
      12. 7.6.12 Ramping Registers
        1. 7.6.12.1 Ramp Limits
          1. Table 36. Field Descriptions
        2. 7.6.12.2 Ramping Triggers, Burst Mode, and RAMP0_RST
          1. Table 37. Field Descriptions
        3. 7.6.12.3 Ramping Configuration
          1. Table 38. Field Descriptions
      13. 7.6.13 Readback Registers
        1. Table 39. Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCin Configuration
      2. 8.1.2 OSCin Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
      5. 8.1.5 Performance Comparison Between 1572 (0x0624) and 3115 (0x0C2B) for Register DBLR_IBIAS_CTRL1 (R25[15:0])
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 11.1.2 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息

7.6.5 N Divider, MASH, and Output Registers

Figure 45. Registers Excluding Address
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R34 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_N[18:16]
R36 PLL_N
R37 MASH
_SEED
_EN		 0 PFD_DLY_SEL 0 0 0 0 0 1 0 0
R38 PLL_DEN[31:16]
R39 PLL_DEN[15:0]
R40 [31:16]
R41 [15:0]
R42 PLL_NUM[31:16]
R43 PLL_NUM[15:0]
R44 0 0 OUTA_PWR OUTB_PD OUTA_PD MASH_RESET_N 0 0 MASH_ORDER
R45 1 1 0 OUTA_MUX OUT_ISET 0 1 1 OUTB_PWR
R46 0 0 0 0 0 1 1 1 1 1 1 1 1 1 OUTB_MUX
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. Field Descriptions

Location Field Type Reset Description
R34[2:0]
R36[15:0]		 PLL_N R/W 100 The PLL_N divider value is in the feedback path and divides the VCO frequency.
R37[15] MASH_SEED_EN R/W 0 Enabling this bit allows the to be applied to shift the phase at the output or optimize spurs.
R37[13:8] PFD_DLY_SEL R/W 2 The PFD_DLY_SEL must be adjusted in accordance to the N-divider value. This is with the functional description for the N-divider.
R38[15:0]
R39[15:0]		 PLL_DEN R/W 4294967295 The fractional denominator.
R40[15:0]
R41[15:0]		 MASH_SEED R/W 0 The initial state of the MASH engine first accumulator. Can be used to shift phase or optimize fractional spurs. Every time the field is programmed, it ADDS this MASH seed to the existing one. To reset it, use the MASH_RESET_N bit.
R42[15:0]
R43[15:0]		 PLL_NUM R/W 0 The fractional numerator
R44[13:8] OUTA_PWR R/W 31 Adjusts output power. Higher numbers give more output power to a point, depending on the pullup component used.
R44[7] OUTB_PD R/W 1 Powers down output B
0: Output B active
1: Output B powered down
R44[6] OUTA_PD R/W 0 Powers down output A
0: Output A Active
1: Output A powered down
R44[5] MASH_RESET_N R/W 1 Resets MASH circuitry to an initial state
0: MASH held in reset. All fractions are ignored
1: Fractional mode enabled. MASH is NOT held in reset.
R44[2:0] MASH_ORDER R/W 0 Sets the MASH order
0: Integer mode
1: First order modulator
2: Second order modulator
3: Third order modulator
4: Fourth order modulator
5-7: Reserved
R45[12:11] OUTA_MUX R/W 1 Selects what signal goes to RFoutA
0: Channel divider
1: VCO
2: VCO2X (Also ensure VCO2X_EN=1)
3: High impedance
R45[10:9] OUT_ISET R/W 0 Setting to a lower value allows slightly higher output power at higher frequencies at the expense of higher current consumption.
0: Maximum output power boost
...
3: No output power boost
R45[5:0] OUTB_PWR R/W 31 Output power setting for RFoutB.
R46[1:0] OUTB_MUX R/W 1 Selects what signal goes to RFoutB
0: Channel divider
1: VCO
2: SysRef (also ensure SYSREF_EN=1)
3: High impedance
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