ZHCSGO9C June   2017  – September 2018 MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 5.11 Typical Characteristics, Current Consumption per Module
    12. 5.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.13.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.13.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.13.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charges
        3. 5.13.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.13.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.13.5.1   Typical Characteristics, Digital Outputs
      6. 5.13.6  LEA
        1. Table 5-13 Low-Energy Accelerator (LEA) Performance
      7. 5.13.7  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      8. 5.13.8  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-20 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-21 eUSCI (I2C Mode) Switching Characteristics
      9. 5.13.9  Segment LCD Controller
        1. Table 5-22 LCD_C Recommended Operating Conditions
        2. Table 5-23 LCD_C Electrical Characteristics
      10. 5.13.10 ADC12_B
        1. Table 5-24 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-25 12-Bit ADC, Timing Parameters
        3. Table 5-26 12-Bit ADC, Linearity Parameters
        4. Table 5-27 12-Bit ADC, Dynamic Performance With External Reference
        5. Table 5-28 12-Bit ADC, Dynamic Performance With Internal Reference
        6. Table 5-29 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. Table 5-30 12-Bit ADC, External Reference
      11. 5.13.11 Reference
        1. Table 5-31 REF, Built-In Reference
      12. 5.13.12 Comparator
        1. Table 5-32 Comparator_E
      13. 5.13.13 FRAM
        1. Table 5-33 FRAM
      14. 5.13.14 USS
        1. Table 5-34 USS Recommended Operating Conditions
        2. Table 5-35 USS LDO
        3. Table 5-36 USSXTAL
        4. Table 5-37 USS HSPLL
        5. Table 5-38 USS SDHS
        6. Table 5-39 USS PHY Output Stage
        7. Table 5-40 USS PHY Input Stage, Multiplexer
        8. Table 5-41 USS PGA
        9. Table 5-42 USS Bias Voltage Generator
      15. 5.13.15 Emulation and Debug
        1. Table 5-43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Ultrasonic Sensing Solution (USS) Module
    4. 6.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 6.5  Operating Modes
      1. 6.5.1 Peripherals in Low-Power Modes
      2. 6.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 6.6  Interrupt Vector Table and Signatures
    7. 6.7  Bootloader (BSL)
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire (SBW) Interface
    9. 6.9  FRAM Controller A (FRCTL_A)
    10. 6.10 RAM
    11. 6.11 Tiny RAM
    12. 6.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 6.13 Peripherals
      1. 6.13.1  Digital I/O
      2. 6.13.2  Oscillator and Clock System (CS)
      3. 6.13.3  Power-Management Module (PMM)
      4. 6.13.4  Hardware Multiplier (MPY)
      5. 6.13.5  Real-Time Clock (RTC_C)
      6. 6.13.6  Measurement Test Interface (MTIF)
      7. 6.13.7  Watchdog Timer (WDT_A)
      8. 6.13.8  System Module (SYS)
      9. 6.13.9  DMA Controller
      10. 6.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
      11. 6.13.11 TA0, TA1, and TA4
      12. 6.13.12 TA2 and TA3
      13. 6.13.13 TB0
      14. 6.13.14 ADC12_B
      15. 6.13.15 USS
      16. 6.13.16 Comparator_E
      17. 6.13.17 CRC16
      18. 6.13.18 CRC32
      19. 6.13.19 AES256 Accelerator
      20. 6.13.20 True Random Seed
      21. 6.13.21 Shared Reference (REF)
      22. 6.13.22 LCD_C
      23. 6.13.23 Embedded Emulation
        1. 6.13.23.1 Embedded Emulation Module (EEM) (S Version)
        2. 6.13.23.2 EnergyTrace++ Technology
    14. 6.14 Input/Output Diagrams
      1. 6.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 6.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 6.14.3  Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      4. 6.14.4  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      5. 6.14.5  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      6. 6.14.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      7. 6.14.7  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      8. 6.14.8  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      9. 6.14.9  Port P6 (P6.0) Input/Output With Schmitt Trigger
      10. 6.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 6.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      12. 6.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      13. 6.14.13 Port P7 (P7.4) Input/Output With Schmitt Trigger
      14. 6.14.14 Port P7 (P7.5) Input/Output With Schmitt Trigger
      15. 6.14.15 Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger
      16. 6.14.16 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      17. 6.14.17 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
      18. 6.14.18 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
      19. 6.14.19 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      20. 6.14.20 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      21. 6.14.21 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 6.15 Device Descriptors (TLV)
    16. 6.16 Memory Map
      1. 6.16.1 Peripheral File Map
    17. 6.17 Identification
      1. 6.17.1 Revision Identification
      2. 6.17.2 Device Identification
      3. 6.17.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1  Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2  External Oscillator (HFXT and LFXT)
      3. 7.1.3  USS Oscillator (USSXT)
      4. 7.1.4  Transducer Connection to the USS Module
      5. 7.1.5  Charge Pump Control of Input Multiplexer
      6. 7.1.6  JTAG
      7. 7.1.7  Reset
      8. 7.1.8  Unused Pins
      9. 7.1.9  General Layout Recommendations
      10. 7.1.10 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
      2. 7.2.2 LCD_C Peripheral
        1. 7.2.2.1 Partial Schematic
        2. 7.2.2.2 Design Requirements
        3. 7.2.2.3 Detailed Design Procedure
        4. 7.2.2.4 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1 入门和下一步
    2. 8.2 器件命名规则
    3. 8.3 工具和软件
    4. 8.4 文档支持
    5. 8.5 相关链接
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息

6.16.1 Peripheral File Map

For complete module register descriptions, see the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide. Table 6-48 lists the base and end addresses of the registers for each peripheral.

Table 6-48 Peripherals

MODULE NAME BASE ADDRESS END ADDRESS
Special Functions (see Table 6-49) 0100h 011Fh
PMM (see Table 6-50) 0120h 013Fh
FRAM Control (see Table 6-51) 0140h 014Fh
CRC (see Table 6-52) 0150h 0157h
RAM Control (see Table 6-53) 0158h 0159h
Watchdog (see Table 6-54) 015Ch 015Dh
CS (see Table 6-55) 0160h 016Fh
SYS (see Table 6-56) 0180h 019Fh
Shared Reference (see Table 6-57) 01B0h 01B1h
Digital I/O (see Table 6-58) 0200h 033Fh
TA0 (see Table 6-59) 0340h 036Fh
TA1 (see Table 6-60) 0380h 03AFh
TB0 (see Table 6-61) 03C0h 03EFh
TA2 (see Table 6-62) 0400h 042Fh
TA3 (see Table 6-63) 0440h 046Fh
RTC_C (see Table 6-64) 04A0h 04BFh
32-Bit Hardware Multiplier (see Table 6-65) 04C0h 04EFh
DMA (see Table 6-66) 0500h 056Fh
MPU Control (see Table 6-67) 05A0h 05AFh
eUSCI_A0 (see Table 6-68) 05C0h 05DFh
eUSCI_A1 (see Table 6-69) 05E0h 05FFh
eUSCI_A2 (see Table 6-70) 0600h 061Fh
eUSCI_A3 (see Table 6-71) 0620h 063Fh
eUSCI_B0 (see Table 6-72) 0640h 066Fh
eUSCI_B1 (see Table 6-73) 0680h 06AFh
TA4 (see Table 6-74) 07C0h 07EFh
ADC12_B (see Table 6-75) 0800h 089Fh
Comparator E (see Table 6-76) 08C0h 08CFh
CRC32 (see Table 6-77) 0980h 09AFh
AES256 (see Table 6-78) 09C0h 09CFh
LCD_C (see Table 6-79) 0A00h 0A5Fh
LEA (see Table 6-80) 0A80h 0AFFh
SAPH(1) (see Table 6-81) 0E00h 0E7Fh
SDHS(1) (see Table 6-82) 0E80h 0EBFh
UUPS(1) (see Table 6-83) 0EC0h 0EDFh
HSPLL(1) (see Table 6-84) 0EE0h 0EFFh
MTIF (see Table 6-85) 0F00h 0F1Fh
(1) Not available in MSP430FR6037, MSP430FR6035, and MSP430FR60371

Table 6-49 Special Functions Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Interrupt Enable SFRIE1 0100h
Interrupt Flag SFRIFG1 0102h
Reset Pin Control SFRRPCR 0104h

Table 6-50 PMM Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
PMM Control 0 PMMCTL0 0120h
PMM Interrupt Flag PMMIFG 012Ah
Power Mode 5 Control 0 PM5CTL0 0130h

Table 6-51 FRAM Control Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
FRAM Controller A Control 0 FRCTL0 0140h
General Control 0 GCCTL0 0144h
General Control 1 GCCTL1 0146h

Table 6-52 CRC Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
CRC Data In CRCDI 0150h
CRC Data In Reverse Byte CRCDIRB 0152h
CRC Initialization and Result CRCINIRES 0154h
CRC Result Reverse CRCRESR 0156h

Table 6-53 RAM Control Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
RAM Controller Control 0 RCCTL0 0158h
RAM Controller Control 1 RCCTL1 015Ah

Table 6-54 Watchdog Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Watchdog Timer Control WDTCTL 015Ch

Table 6-55 CS Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Clock System Control 0 CSCTL0 0160h
Clock System Control 1 CSCTL1 0162h
Clock System Control 2 CSCTL2 0164h
Clock System Control 3 CSCTL3 0166h
Clock System Control 4 CSCTL4 0168h
Clock System Control 5 CSCTL5 016Ah
Clock System Control 6 CSCTL6 016Ch

Table 6-56 SYS Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
System Control SYSCTL 0180h
JTAG Mailbox Control SYSJMBC 0186h
JTAG Mailbox Input SYSJMBI0 0188h
JTAG Mailbox Input SYSJMBI1 018Ah
JTAG Mailbox Output SYSJMBO0 018Ch
JTAG Mailbox Output SYSJMBO1 018Eh
User NMI Vector Generator SYSUNIV 019Ah
System NMI Vector Generator SYSSNIV 019Ch
Reset Vector Generator SYSRSTIV 019Eh

Table 6-57 Shared Reference Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
REF Control 0 REFCTL0 01B0h

Table 6-58 Digital I/O Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Port A Input PAIN 0200h
Port 1 Input P1IN 0200h
Port 2 Input P2IN 0201h
Port A Output PAOUT 0202h
Port 1 Output P1OUT 0202h
Port 2 Output P2OUT 0203h
Port A Direction PADIR 0204h
Port 1 Direction P1DIR 0204h
Port 2 Direction P2DIR 0205h
Port A Resistor Enable PAREN 0206h
Port 1 Resistor Enable P1REN 0206h
Port 2 Resistor Enable P2REN 0207h
Port A Select 0 PASEL0 020Ah
Port 1 Select 0 P1SEL0 020Ah
Port 2 Select 0 P2SEL0 020Bh
Port A Select 1 PASEL1 020Ch
Port 1 Select 1 P1SEL1 020Ch
Port 2 Select 1 P2SEL1 020Dh
Port 1 Interrupt Vector P1IV 020Eh
Port A Complement Select PASELC 0216h
Port 1 Complement Select P1SELC 0216h
Port 2 Complement Select P2SELC 0217h
Port A Interrupt Edge Select PAIES 0218h
Port 1 Interrupt Edge Select P1IES 0218h
Port 2 Interrupt Edge Select P2IES 0219h
Port A Interrupt Enable PAIE 021Ah
Port 1 Interrupt Enable P1IE 021Ah
Port 2 Interrupt Enable P2IE 021Bh
Port A Interrupt Flag PAIFG 021Ch
Port 1 Interrupt Flag P1IFG 021Ch
Port 2 Interrupt Flag P2IFG 021Dh
Port 2 Interrupt Vector P2IV 021Eh
Port B Input PBIN 0220h
Port 3 Input P3IN 0220h
Port 4 Input P4IN 0221h
Port B Output PBOUT 0222h
Port 3 Output P3OUT 0222h
Port 4 Output P4OUT 0223h
Port B Direction PBDIR 0224h
Port 3 Direction P3DIR 0224h
Port 4 Direction P4DIR 0225h
Port B Resistor Enable PBREN 0226h
Port 3 Resistor Enable P3REN 0226h
Port 4 Resistor Enable P4REN 0227h
Port B Select 0 PBSEL0 022Ah
Port 3 Select 0 P3SEL0 022Ah
Port 4 Select 0 P4SEL0 022Bh
Port B Select 1 PBSEL1 022Ch
Port 3 Select 1 P3SEL1 022Ch
Port 4 Select 1 P4SEL1 022Dh
Port 3 Interrupt Vector P3IV 022Eh
Port B Complement Select PBSELC 0236h
Port 3 Complement Select P3SELC 0236h
Port 4 Complement Select P4SELC 0237h
Port B Interrupt Edge Select PBIES 0238h
Port 3 Interrupt Edge Select P3IES 0238h
Port 4 Interrupt Edge Select P4IES 0239h
Port B Interrupt Enable PBIE 023Ah
Port 3 Interrupt Enable P3IE 023Ah
Port 4 Interrupt Enable P4IE 023Bh
Port B Interrupt Flag PBIFG 023Ch
Port 3 Interrupt Flag P3IFG 023Ch
Port 4 Interrupt Flag P4IFG 023Dh
Port 4 Interrupt Vector P4IV 023Eh
Port C Input PCIN 0240h
Port 5 Input P5IN 0240h
Port 6 Input P6IN 0241h
Port C Output PCOUT 0242h
Port 5 Output P5OUT 0242h
Port 6 Output P6OUT 0243h
Port C Direction PCDIR 0244h
Port 5 Direction P5DIR 0244h
Port 6 Direction P6DIR 0245h
Port C Resistor Enable PCREN 0246h
Port 5 Resistor Enable P5REN 0246h
Port 6 Resistor Enable P6REN 0247h
Port C Select 0 PCSEL0 024Ah
Port 5 Select 0 P5SEL0 024Ah
Port 6 Select 0 P6SEL0 024Bh
Port C Select 1 PCSEL1 024Ch
Port 5 Select 1 P5SEL1 024Ch
Port 6 Select 1 P6SEL1 024Dh
Port 5 Interrupt Vector P5IV 024Eh
Port C Complement Select PCSELC 0256h
Port 5 Complement Select P5SELC 0256h
Port 6 Complement Select P6SELC 0257h
Port C Interrupt Edge Select PCIES 0258h
Port 5 Interrupt Edge Select P5IES 0258h
Port 6 Interrupt Edge Select P6IES 0259h
Port C Interrupt Enable PCIE 025Ah
Port 5 Interrupt Enable P5IE 025Ah
Port 6 Interrupt Enable P6IE 025Bh
Port C Interrupt Flag PCIFG 025Ch
Port 5 Interrupt Flag P5IFG 025Ch
Port 6 Interrupt Flag P6IFG 025Dh
Port 6 Interrupt Vector P6IV 025Eh
Port D Input PDIN 0260h
Port 7 Input P7IN 0260h
Port 8 Input P8IN 0261h
Port D Output PDOUT 0262h
Port 7 Output P7OUT 0262h
Port 8 Output P8OUT 0263h
Port D Direction PDDIR 0264h
Port 7 Direction P7DIR 0264h
Port 8 Direction P8DIR 0265h
Port D Resistor Enable PDREN 0266h
Port 7 Resistor Enable P7REN 0266h
Port 8 Resistor Enable P8REN 0267h
Port D Select 0 PDSEL0 026Ah
Port 7 Select 0 P7SEL0 026Ah
Port 8 Select 0 P8SEL0 026Bh
Port D Select 1 PDSEL1 026Ch
Port 7 Select 1 P7SEL1 026Ch
Port 8 Select 1 P8SEL1 026Dh
Port 7 Interrupt Vector P7IV 026Eh
Port D Complement Select PDSELC 0276h
Port 7 Complement Select P7SELC 0276h
Port 8 Complement Select P8SELC 0277h
Port D Interrupt Edge Select PDIES 0278h
Port 7 Interrupt Edge Select P7IES 0278h
Port 8 Interrupt Edge Select P8IES 0279h
Port D Interrupt Enable PDIE 027Ah
Port 7 Interrupt Enable P7IE 027Ah
Port 8 Interrupt Enable P8IE 027Bh
Port D Interrupt Flag PDIFG 027Ch
Port 7 Interrupt Flag P7IFG 027Ch
Port 8 Interrupt Flag P8IFG 027Dh
Port 8 Interrupt Vector P8IV 027Eh
Port E Input PEIN 0280h
Port 9 Input P9IN 0280h
Port E Output PEOUT 0282h
Port 9 Output P9OUT 0282h
Port E Direction PEDIR 0284h
Port 9 Direction P9DIR 0284h
Port E Resistor Enable PEREN 0286h
Port 9 Resistor Enable P9REN 0286h
Port E Select 0 PESEL0 028Ah
Port 9 Select 0 P9SEL0 028Ah
Port E Select 1 PESEL1 028Ch
Port 9 Select 1 P9SEL1 028Ch
Port 9 Interrupt Vector P9IV 028Eh
Port E Complement Select PESELC 0296h
Port 9 Complement Select P9SELC 0296h
Port E Interrupt Edge Select PEIES 0298h
Port 9 Interrupt Edge Select P9IES 0298h
Port E Interrupt Enable PEIE 029Ah
Port 9 Interrupt Enable P9IE 029Ah
Port E Interrupt Flag PEIFG 029Ch
Port 9 Interrupt Flag P9IFG 029Ch
Port J Input PJIN 0320h
Port J Output PJOUT 0322h
Port J Direction PJDIR 0324h
Port J Resistor Enable PJREN 0326h
Port J Select 0 PJSEL0 032Ah
Port J Select 1 PJSEL1 032Ch
Port J Complement Select PJSELC 0336h

Table 6-59 TA0 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Timer_A0 Control TA0CTL 0340h
Timer_A0 Capture/Compare Control TA0CCTL0 0342h
Timer_A0 Capture/Compare Control TA0CCTL1 0344h
Timer_A0 Capture/Compare Control TA0CCTL2 0346h
Timer_A0 Counter TA0R 0350h
Timer_A0 Capture/Compare TA0CCR0 0352h
Timer_A0 Capture/Compare TA0CCR1 0354h
Timer_A0 Capture/Compare TA0CCR2 0356h
Timer_A0 Expansion 0 TA0EX0 0360h
Timer_A0 Interrupt Vector TA0IV 036Eh

Table 6-60 TA1 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Timer_A1 Control TA1CTL 0380h
Timer_A1 Capture/Compare Control TA1CCTL0 0382h
Timer_A1 Capture/Compare Control TA1CCTL1 0384h
Timer_A1 Capture/Compare Control TA1CCTL2 0386h
Timer_A1 Counter TA1R 0390h
Timer_A1 Capture/Compare TA1CCR0 0392h
Timer_A1 Capture/Compare TA1CCR1 0394h
Timer_A1 Capture/Compare TA1CCR2 0396h
Timer_A1 Expansion 0 TA1EX0 03A0h
Timer_A1 Interrupt Vector TA1IV 03AEh

Table 6-61 TB0 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Timer_B0 Control TB0CTL 03C0h
Timer_B0 Capture/Compare Control TB0CCTL0 03C2h
Timer_B0 Capture/Compare Control TB0CCTL1 03C4h
Timer_B0 Capture/Compare Control TB0CCTL2 03C6h
Timer_B0 Capture/Compare Control TB0CCTL3 03C8h
Timer_B0 Capture/Compare Control TB0CCTL4 03CAh
Timer_B0 Capture/Compare Control TB0CCTL5 03CCh
Timer_B0 Capture/Compare Control TB0CCTL6 03CEh
Timer_B0 Counter TB0R 03D0h
Timer_B0 Capture/Compare TB0CCR0 03D2h
Timer_B0 Capture/Compare TB0CCR1 03D4h
Timer_B0 Capture/Compare TB0CCR2 03D6h
Timer_B0 Capture/Compare TB0CCR3 03D8h
Timer_B0 Capture/Compare TB0CCR4 03DAh
Timer_B0 Capture/Compare TB0CCR5 03DCh
Timer_B0 Capture/Compare TB0CCR6 03DEh
Timer_B0 Expansion 0 TB0EX0 03E0h
Timer_B0 Interrupt Vector TB0IV 03EEh

Table 6-62 TA2 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Timer_A2 Control TA2CTL 0400h
Timer_A2 Capture/Compare Control TA2CCTL0 0402h
Timer_A2 Capture/Compare Control TA2CCTL1 0404h
Timer_A2 Counter TA2R 0410h
Timer_A2 Capture/Compare TA2CCR0 0412h
Timer_A2 Capture/Compare TA2CCR1 0414h
Timer_A2 Expansion 0 TA2EX0 0420h
Timer_A2 Interrupt Vector TA2IV 042Eh

Table 6-63 TA3 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Timer_A3 Control TA3CTL 0440h
Timer_A3 Capture/Compare Control TA3CCTL0 0442h
Timer_A3 Capture/Compare Control TA3CCTL1 0444h
Timer_A3 Counter TA3R 0450h
Timer_A3 Capture/Compare TA3CCR0 0452h
Timer_A3 Capture/Compare TA3CCR1 0454h
Timer_A3 Expansion 0 TA3EX0 0460h
Timer_A3 Interrupt Vector TA3IV 046Eh

Table 6-64 RTC_C Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Real-Time Clock Control 0 RTCCTL0 04A0h
Real-Time Clock Control 1, 3 RTCCTL13 04A2h
Real-Time Clock Offset Calibration RTCOCAL 04A4h
Real-Time Clock Temperature Compensation RTCTCMP 04A6h
Real-Time Clock Prescale Timer 0 Control RTCPS0CTL 04A8h
Real-Time Clock Prescale Timer 1 Control RTCPS1CTL 04AAh
Real-Time Clock Prescale Timer Counter RTCPS 04ACh
Prescale Timer 0 Counter Value RT0PS 04ACh
Prescale Timer 1 Counter Value RT1PS 04ADh
Real-Time Clock Interrupt Vector RTCIV 04AEh
Real-Time Clock Seconds and Minutes RTCTIM0 04B0h
Real-Time Clock Hour, Day of Week RTCTIM1 04B2h
Real-Time Clock Date RTCDATE 04B4h
Real-Time Clock Year RTCYEAR 04B6h
Real-Time Clock Minute and Hour RTCAMINHR 04B8h
Real-Time Clock Alarm Day of Week and Day RTCADOWDAY 04BAh
Binary-to-BCD Conversion BIN2BCD 04BCh
BCD-to-Binary Conversion BCD2BIN 04BEh

Table 6-65 32-Bit Hardware Multiplier Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
16-bit operand one – multiply MPY 04C0h
16-bit operand one – signed multiply MPYS 04C2h
16-bit operand one – multiply accumulate MAC 04C4h
16-bit operand one – signed multiply accumulate MACS 04C6h
16-bit operand two OP2 04C8h
16x16-bit result low word RESLO 04CAh
16x16-bit result high word RESHI 04CCh
16x16-bit sum extension SUMEXT 04CEh
32-bit operand 1 – multiply – low word MPY32L 04D0h
32-bit operand 1 – multiply – high word MPY32H 04D2h
32-bit operand 1 – signed multiply – low word MPYS32L 04D4h
32-bit operand 1 – signed multiply – high word MPYS32H 04D6h
32-bit operand 1 – multiply accumulate – low word MAC32L 04D8h
32-bit operand 1 – multiply accumulate – high word MAC32H 04DAh
32-bit operand 1 – signed multiply accumulate – low word MACS32L 04DCh
32-bit operand 1 – signed multiply accumulate – high word MACS32H 04DEh
32-bit operand 2 – low word OP2L 04E0h
32-bit operand 2 – high word OP2H 04E2h
32x32-bit result 0 – least significant word RES0 04E4h
32x32-bit result 1 RES1 04E6h
32x32-bit result 2 RES2 04E8h
32x32-bit result 3 – most significant word RES3 04EAh
MPY32 control 0 MPY32CTL0 04ECh

Table 6-66 DMA Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
DMA Control 0 DMACTL0 0500h
DMA Control 1 DMACTL1 0502h
DMA Control 2 DMACTL2 0504h
DMA Control 4 DMACTL4 0508h
DMA Interrupt Vector DMAIV 050Eh
DMA Channel 0 Control DMA0CTL 0510h
DMA Channel 0 Source Address DMA0SA 0512h
DMA Channel 0 Destination Address DMA0DA 0516h
DMA Channel 0 Transfer Size DMA0SZ 051Ah
DMA Channel 1 Control DMA1CTL 0520h
DMA Channel 1 Source Address DMA1SA 0522h
DMA Channel 1 Destination Address DMA1DA 0526h
DMA Channel 1 Transfer Size DMA1SZ 052Ah
DMA Channel 2 Control DMA2CTL 0530h
DMA Channel 2 Source Address DMA2SA 0532h
DMA Channel 2 Destination Address DMA2DA 0536h
DMA Channel 2 Transfer Size DMA2SZ 053Ah
DMA Channel 3 Control DMA3CTL 0540h
DMA Channel 3 Source Address DMA3SA 0542h
DMA Channel 3 Destination Address DMA3DA 0546h
DMA Channel 3 Transfer Size DMA3SZ 054Ah
DMA Channel 4 Control DMA4CTL 0550h
DMA Channel 4 Source Address DMA4SA 0552h
DMA Channel 4 Destination Address DMA4DA 0556h
DMA Channel 4 Transfer Size DMA4SZ 055Ah
DMA Channel 5 Control DMA5CTL 0560h
DMA Channel 5 Source Address DMA5SA 0562h
DMA Channel 5 Destination Address DMA5DA 0566h
DMA Channel 5 Transfer Size DMA5SZ 056Ah

Table 6-67 MPU Control Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Memory Protection Unit Control 0 MPUCTL0 05A0h
Memory Protection Unit Control 1 MPUCTL1 05A2h
Memory Protection Unit Segmentation Border 2 Register MPUSEGB2 05A4h
Memory Protection Unit Segmentation Border 1 Register MPUSEGB1 05A6h
Memory Protection Unit Segmentation Access Management Register MPUSAM 05A8h
Memory Protection Unit IP Control 0 Register MPUIPC0 05AAh
Memory Protection Unit IP Encapsulation Segment Border 2 Register MPUIPSEGB2 05ACh
Memory Protection Unit IP Encapsulation Segment Border 1 Register MPUIPSEGB1 05AEh

Table 6-68 eUSCI_A0 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
eUSCI_A0 Control Word Register 0 UCA0CTLW0 05C0h
eUSCI_A0 Control Word Register 1 UCA0CTLW1 05C2h
eUSCI_A0 Baud Rate Control Word UCA0BRW 05C6h
eUSCI_A0 Modulation Control Word UCA0MCTLW 05C8h
eUSCI_A0 Status Register UCA0STATW 05CAh
eUSCI_A0 Receive Buffer UCA0RXBUF 05CCh
eUSCI_A0 Transmit Buffer UCA0TXBUF 05CEh
eUSCI_A0 Auto Baud Rate Control UCA0ABCTL 05D0h
eUSCI_A0 IrDA Control Word UCA0IRCTL 05D2h
eUSCI_A0 Interrupt Enable UCA0IE 05DAh
eUSCI_A0 Interrupt Flag UCA0IFG 05DCh
eUSCI_A0 Interrupt Vector UCA0IV 05DEh

Table 6-69 eUSCI_A1 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
eUSCI_A1 Control Word Register 0 UCA1CTLW0 05E0h
eUSCI_A1 Control Word Register 1 UCA1CTLW1 05E2h
eUSCI_A1 Baud Rate Control Word UCA1BRW 05E6h
eUSCI_A1 Modulation Control Word UCA1MCTLW 05E8h
eUSCI_A1 Status Register UCA1STATW 05EAh
eUSCI_A1 Receive Buffer UCA1RXBUF 05ECh
eUSCI_A1 Transmit Buffer UCA1TXBUF 05EEh
eUSCI_A1 Auto Baud Rate Control UCA1ABCTL 05F0h
eUSCI_A1 IrDA Control Word UCA1IRCTL 05F2h
eUSCI_A1 Interrupt Enable UCA1IE 05FAh
eUSCI_A1 Interrupt Flag UCA1IFG 05FCh
eUSCI_A1 Interrupt Vector UCA1IV 05FEh

Table 6-70 eUSCI_A2 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
eUSCI_A2 Control Word Register 0 UCA2CTLW0 0600h
eUSCI_A2 Control Word Register 1 UCA2CTLW1 0602h
eUSCI_A2 Baud Rate Control Word UCA2BRW 0606h
eUSCI_A2 Modulation Control Word UCA2MCTLW 0608h
eUSCI_A2 Status Register UCA2STATW 060Ah
eUSCI_A2 Receive Buffer UCA2RXBUF 060Ch
eUSCI_A2 Transmit Buffer UCA2TXBUF 060Eh
eUSCI_A2 Auto Baud Rate Control UCA2ABCTL 0610h
eUSCI_A2 IrDA Control Word UCA2IRCTL 0612h
eUSCI_A2 Interrupt Enable UCA2IE 061Ah
eUSCI_A2 Interrupt Flag UCA2IFG 061Ch
eUSCI_A2 Interrupt Vector UCA2IV 061Eh

Table 6-71 eUSCI_A3 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
eUSCI_A3 Control Word Register 0 UCA3CTLW0 0620h
eUSCI_A3 Control Word Register 1 UCA3CTLW1 0622h
eUSCI_A3 Baud Rate Control Word UCA3BRW 0626h
eUSCI_A3 Modulation Control Word UCA3MCTLW 0628h
eUSCI_A3 Status Register UCA3STATW 062Ah
eUSCI_A3 Receive Buffer UCA3RXBUF 062Ch
eUSCI_A3 Transmit Buffer UCA3TXBUF 062Eh
eUSCI_A3 Auto Baud Rate Control UCA3ABCTL 0630h
eUSCI_A3 IrDA Control Word UCA3IRCTL 0632h
eUSCI_A3 Interrupt Enable UCA3IE 063Ah
eUSCI_A3 Interrupt Flag UCA3IFG 063Ch
eUSCI_A3 Interrupt Vector UCA3IV 063Eh

Table 6-72 eUSCI_B0 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
eUSCI_B0 Control Word Register 0 UCB0CTLW0 0640h
eUSCI_B0 Control Word Register 1 UCB0CTLW1 0642h
eUSCI_B0 Baud Rate Control Word UCB0BRW 0646h
eUSCI_B0 Status Register UCB0STATW 0648h
eUSCI_B0 Byte Counter Threshold UCB0TBCNT 064Ah
eUSCI_B0 Receive Buffer UCB0RXBUF 064Ch
eUSCI_B0 Transmit Buffer UCB0TXBUF 064Eh
eUSCI_B0 I2C Own Address 0 UCB0I2COA0 0654h
eUSCI_B0 I2C Own Address 1 UCB0I2COA1 0656h
eUSCI_B0 I2C Own Address 2 UCB0I2COA2 0658h
eUSCI_B0 I2C Own Address 3 UCB0I2COA3 065Ah
eUSCI_B0 I2C Received Address UCB0ADDRX 065Ch
eUSCI_B0 I2C Address Mask UCB0ADDMASK 065Eh
eUSCI_B0 I2C Slave Address UCB0I2CSA 0660h
eUSCI_B0 Interrupt Enable UCB0IE 066Ah
eUSCI_B0 Interrupt Flag UCB0IFG 066Ch
eUSCI_B0 Interrupt Vector UCB0IV 066Eh

Table 6-73 eUSCI_B1 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
eUSCI_B1 Control Word Register 0 UCB1CTLW0 0680h
eUSCI_B1 Control Word Register 1 UCB1CTLW1 0682h
eUSCI_B1 Baud Rate Control Word UCB1BRW 0686h
eUSCI_B1 Status Register UCB1STATW 0688h
eUSCI_B1 Byte Counter Threshold UCB1TBCNT 068Ah
eUSCI_B1 Receive Buffer UCB1RXBUF 068Ch
eUSCI_B1 Transmit Buffer UCB1TXBUF 068Eh
eUSCI_B1 I2C Own Address 0 UCB1I2COA0 0694h
eUSCI_B1 I2C Own Address 1 UCB1I2COA1 0696h
eUSCI_B1 I2C Own Address 2 UCB1I2COA2 0698h
eUSCI_B1 I2C Own Address 3 UCB1I2COA3 069Ah
eUSCI_B1 I2C Received Address UCB1ADDRX 069Ch
eUSCI_B1 I2C Address Mask UCB1ADDMASK 069Eh
eUSCI_B1 I2C Slave Address UCB1I2CSA 06A0h
eUSCI_B1 Interrupt Enable UCB1IE 06AAh
eUSCI_B1 Interrupt Flag UCB1IFG 06ACh
eUSCI_B1 Interrupt Vector UCB1IV 06AEh

Table 6-74 TA4 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Timer_A4 Control TA4CTL 07C0h
Timer_A4 Capture/Compare Control TA4CCTL0 07C2h
Timer_A4 Capture/Compare Control TA4CCTL1 07C4h
Timer_A4 Counter TA4R 07D0h
Timer_A4 Capture/Compare TA4CCR0 07D2h
Timer_A4 Capture/Compare TA4CCR1 07D4h
Timer_A4 Expansion 0 TA4EX0 07E0h
Timer_A4 Interrupt Vector TA4IV 07EEh

Table 6-75 ADC12_B Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
ADC12_B Control 0 ADC12CTL0 0800h
ADC12_B Control 1 ADC12CTL1 0802h
ADC12_B Control 2 ADC12CTL2 0804h
ADC12_B Control 3 ADC12CTL3 0806h
ADC12_B Window Comparator Low Threshold Register ADC12LO 0808h
ADC12_B Window Comparator High Threshold Register ADC12HI 080Ah
ADC12_B Interrupt Flag 0 ADC12IFGR0 080Ch
ADC12_B Interrupt Flag 1 ADC12IFGR1 080Eh
ADC12_B Interrupt Flag 2 ADC12IFGR2 0810h
ADC12_B Interrupt Enable 0 ADC12IER0 0812h
ADC12_B Interrupt Enable 1 ADC12IER1 0814h
ADC12_B Interrupt Enable 2 ADC12IER2 0816h
ADC12_B Interrupt Vector ADC12IV 0818h
ADC12_B Memory Control 0 ADC12MCTL0 0820h
ADC12_B Memory Control 1 ADC12MCTL1 0822h
ADC12_B Memory Control 2 ADC12MCTL2 0824h
ADC12_B Memory Control 3 ADC12MCTL3 0826h
ADC12_B Memory Control 4 ADC12MCTL4 0828h
ADC12_B Memory Control 5 ADC12MCTL5 082Ah
ADC12_B Memory Control 6 ADC12MCTL6 082Ch
ADC12_B Memory Control 7 ADC12MCTL7 082Eh
ADC12_B Memory Control 8 ADC12MCTL8 0830h
ADC12_B Memory Control 9 ADC12MCTL9 0832h
ADC12_B Memory Control 10 ADC12MCTL10 0834h
ADC12_B Memory Control 11 ADC12MCTL11 0836h
ADC12_B Memory Control 12 ADC12MCTL12 0838h
ADC12_B Memory Control 13 ADC12MCTL13 083Ah
ADC12_B Memory Control 14 ADC12MCTL14 083Ch
ADC12_B Memory Control 15 ADC12MCTL15 083Eh
ADC12_B Memory Control 16 ADC12MCTL16 0840h
ADC12_B Memory Control 17 ADC12MCTL17 0842h
ADC12_B Memory Control 18 ADC12MCTL18 0844h
ADC12_B Memory Control 19 ADC12MCTL19 0846h
ADC12_B Memory Control 20 ADC12MCTL20 0848h
ADC12_B Memory Control 21 ADC12MCTL21 084Ah
ADC12_B Memory Control 22 ADC12MCTL22 084Ch
ADC12_B Memory Control 23 ADC12MCTL23 084Eh
ADC12_B Memory Control 24 ADC12MCTL24 0850h
ADC12_B Memory Control 25 ADC12MCTL25 0852h
ADC12_B Memory Control 26 ADC12MCTL26 0854h
ADC12_B Memory Control 27 ADC12MCTL27 0856h
ADC12_B Memory Control 28 ADC12MCTL28 0858h
ADC12_B Memory Control 29 ADC12MCTL29 085Ah
ADC12_B Memory Control 30 ADC12MCTL30 085Ch
ADC12_B Memory Control 31 ADC12MCTL31 085Eh
ADC12_B Memory 0 ADC12MEM0 0860h
ADC12_B Memory 1 ADC12MEM1 0862h
ADC12_B Memory 2 ADC12MEM2 0864h
ADC12_B Memory 3 ADC12MEM3 0866h
ADC12_B Memory 4 ADC12MEM4 0868h
ADC12_B Memory 5 ADC12MEM5 086Ah
ADC12_B Memory 6 ADC12MEM6 086Ch
ADC12_B Memory 7 ADC12MEM7 086Eh
ADC12_B Memory 8 ADC12MEM8 0870h
ADC12_B Memory 9 ADC12MEM9 0872h
ADC12_B Memory 10 ADC12MEM10 0874h
ADC12_B Memory 11 ADC12MEM11 0876h
ADC12_B Memory 12 ADC12MEM12 0878h
ADC12_B Memory 13 ADC12MEM13 087Ah
ADC12_B Memory 14 ADC12MEM14 087Ch
ADC12_B Memory 15 ADC12MEM15 087Eh
ADC12_B Memory 16 ADC12MEM16 0880h
ADC12_B Memory 17 ADC12MEM17 0882h
ADC12_B Memory 18 ADC12MEM18 0884h
ADC12_B Memory 19 ADC12MEM19 0886h
ADC12_B Memory 20 ADC12MEM20 0888h
ADC12_B Memory 21 ADC12MEM21 088Ah
ADC12_B Memory 22 ADC12MEM22 088Ch
ADC12_B Memory 23 ADC12MEM23 088Eh
ADC12_B Memory 24 ADC12MEM24 0890h
ADC12_B Memory 25 ADC12MEM25 0892h
ADC12_B Memory 26 ADC12MEM26 0894h
ADC12_B Memory 27 ADC12MEM27 0896h
ADC12_B Memory 28 ADC12MEM28 0898h
ADC12_B Memory 29 ADC12MEM29 089Ah
ADC12_B Memory 30 ADC12MEM30 089Ch
ADC12_B Memory 31 ADC12MEM31 089Eh

Table 6-76 Comparator_E Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Comparator Control Register 0 CECTL0 08C0h
Comparator Control Register 1 CECTL1 08C2h
Comparator Control Register 2 CECTL2 08C4h
Comparator Control Register 3 CECTL3 08C6h
Comparator Interrupt Control CEINT 08CCh
Comparator Interrupt Vector Word CEIV 08CEh

Table 6-77 CRC32 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
CRC32 Data Input Word 0 CRC32DIW0 0980h
CRC32 Data Input Word 1 CRC32DIW1 0982h
CRC32 Data In Reverse Word 1 CRC32DIRBW1 0984h
CRC32 Data In Reverse Word 0 CRC32DIRBW0 0986h
CRC32 Initialization and Result Word 0 CRC32INIRESW0 0988h
CRC32 Initialization and Result Word 1 CRC32INIRESW1 098Ah
CRC32 Result Reverse Word 1 CRC32RESRW1 098Ch
CRC32 Result Reverse Word 0 CRC32RESRW0 098Eh
CRC16 Data Input CRC16DIW0 0990h
CRC16 Data In Reverse CRC16DIRBW0 0996h
CRC16 Init and Result CRC16INIRESW0 0998h
CRC16 Result Reverse CRC16RESRW0 099Eh

Table 6-78 AES256 Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
AES Accelerator Control 0 AESACTL0 09C0h
AES Accelerator Control 1 AESACTL1 09C2h
AES Accelerator Status AESASTAT 09C4h
AES Accelerator Key AESAKEY 09C6h
AES Accelerator Data In AESADIN 09C8h
AES Accelerator Data Out AESADOUT 09CAh
AES Accelerator XORed Data In AESAXDIN 09CCh
AES Accelerator XORed Data In AESAXIN 09CEh

Table 6-79 LCD_C Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
LCD_C control 0 LCDCCTL0 0A00h
LCD_C control 1 LCDCCTL1 0A02h
LCD_C blinking control LCDCBLKCTL 0A04h
LCD_C memory control LCDCMEMCTL 0A06h
LCD_C Voltage Control LCDCVCTL 0A08h
LCD_C port control 0 LCDCPCTL0 0A0Ah
LCD_C port control 1 LCDCPCTL1 0A0Ch
LCD_C port control 2 (≥256 segments) LCDCPCTL2 0A0Eh
LCD_C port control 3 (384 segments) LCDCPCTL3 0A10h
LCD_C charge pump control LCDCCPCTL 0A12h
LCD_C interrupt vector LCDCIV 0A1Eh
LCDMX = 0 ... 4
LCD memory 1 LCDM1 0A20h
LCD memory 2 LCDM2 0A21h
LCD memory 3 LCDM3 0A22h
LCD memory 4 LCDM4 0A23h
LCD memory 5 LCDM5 0A24h
LCD memory 6 LCDM6 0A25h
LCD memory 7 LCDM7 0A26h
LCD memory 8 LCDM8 0A27h
LCD memory 9 LCDM9 0A28h
LCD memory 10 LCDM10 0A29h
LCD memory 11 LCDM11 0A2Ah
LCD memory 12 LCDM12 0A2Bh
LCD memory 13 LCDM13 0A2Ch
LCD memory 14 LCDM14 0A2Dh
LCD memory 15 LCDM15 0A2Eh
LCD memory 16 LCDM16 0A2Fh
LCD memory 17 LCDM17 0A30h
LCD memory 18 LCDM18 0A31h
LCD memory 19 LCDM19 0A32h
LCD memory 20 LCDM20 0A33h
LCD blinking memory 1 LCDM33_LCDBM1 0A40h
LCD blinking memory 2 LCDM34_LCDBM2 0A41h
LCD blinking memory 3 LCDM35_LCDBM3 0A42h
LCD blinking memory 4 LCDM36_LCDBM4 0A43h
LCD blinking memory 5 LCDM37_LCDBM5 0A44h
LCD blinking memory 6 LCDM38_LCDBM6 0A45h
LCD blinking memory 7 LCDM39_LCDBM7 0A46h
LCD blinking memory 8 LCDM40_LCDBM8 0A47h
LCD blinking memory 9 LCDM41_LCDBM9 0A48h
LCD blinking memory 10 LCDM42_LCDBM10 0A49h
LCD blinking memory 11 LCDM43_LCDBM11 0A4Ah
LCD blinking memory 11 LCDM44_LCDBM12 0A4Bh
LCD blinking memory 13 LCDM45_LCDBM13 0A4Ch
LCD blinking memory 14 LCDM46_LCDBM14 0A4Dh
LCD blinking memory 15 LCDM47_LCDBM15 0A4Eh
LCD blinking memory 16 LCDM48_LCDBM16 0A4Fh
LCD blinking memory 17 LCDM49_LCDBM17 0A50h
LCD blinking memory 18 LCDM50_LCDBM18 0A51h
LCD blinking memory 19 LCDM51_LCDBM19 0A52h
LCD blinking memory 20 LCDM52_LCDBM20 0A53h
LCDMX = 5 ... 8
LCD memory 1 LCDM1 0A20h
LCD memory 2 LCDM2 0A21h
LCD memory 3 LCDM3 0A22h
LCD memory 4 LCDM4 0A23h
LCD memory 5 LCDM5 0A24h
LCD memory 6 LCDM6 0A25h
LCD memory 7 LCDM7 0A26h
LCD memory 8 LCDM8 0A27h
LCD memory 9 LCDM9 0A28h
LCD memory 10 LCDM10 0A29h
LCD memory 11 LCDM11 0A2Ah
LCD memory 12 LCDM12 0A2Bh
LCD memory 13 LCDM13 0A2Ch
LCD memory 14 LCDM14 0A2Dh
LCD memory 15 LCDM15 0A2Eh
LCD memory 16 LCDM16 0A2Fh
LCD memory 17 LCDM17 0A30h
LCD memory 18 LCDM18 0A31h
LCD memory 19 LCDM19 0A32h
LCD memory 20 LCDM20 0A33h
LCD memory 21 LCDM21 0A34h
LCD memory 22 LCDM22 0A35h
LCD memory 23 LCDM23 0A36h
LCD memory 24 LCDM24 0A37h
LCD memory 25 LCDM25 0A38h
LCD memory 26 LCDM26 0A39h
LCD memory 27 LCDM27 0A3Ah
LCD memory 28 LCDM28 0A3Bh
LCD memory 29 LCDM29 0A3Ch
LCD memory 30 LCDM30 0A3Dh
LCD memory 31 LCDM31 0A3Eh
LCD memory 32 LCDM32 0A3Fh
LCD memory 33 LCDM33_LCDBM1 0A40h
LCD memory 34 LCDM34_LCDBM2 0A41h
LCD memory 35 LCDM35_LCDBM3 0A42h
LCD memory 36 LCDM36_LCDBM4 0A43h

Table 6-80 LEA Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
LEA Capability Register LEACAP 0A80h
Configuration Register 0 LEACNF0 0A84h
Configuration Register 1 LEACNF1 0A88h
Configuration Register 2 LEACNF2 0A8Ch
Memory Bottom Register LEAMB 0A90h
Memory Top Register LEAMT 0A94h
Code Memory Access LEACMA 0A98h
Code Memory Control LEACMCTL 0A9Ch
LEA Command Status LEACMDSTAT 0AA8h
LEA Source 1 Status LEAS1STAT 0AACh
LEA Source 0 Status LEAS0STAT 0AB0h
LEA Result Status LEADSTSTAT 0AB4h
PM Control Register LEAPMCTL 0AC0h
PM Result Register LEAPMDST 0AC4h
PM Source 1 Register LEAPMS1 0AC8h
PM Source 0 Register LEAPMS0 0ACCh
PM Command Buffer LEAPMCB 0AD0h
Interrupt Flag and Set LEAIFGSET 0AF0h
Interrupt Enable LEAIE 0AF4h
Interrupt Flag and Clear LEAIFG 0AF8h
Interrupt Vector LEAIV 0AFCh

Table 6-81 SAPH Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Interrupt Index SAPHIIDX 0E00h
Masked Interrupt Satus SAPHMIS 0E02h
Raw Interrupt Status SAPHRIS 0E04h
Interrupt Mask SAPHIMSC 0E06h
Interrupt Clear SAPHICR 0E08h
Interrupt Set SAPHISR 0E0Ah
Module-Descriptor Low Word SAPHDESCLO 0E0Ch
Module-Descriptor High Word SAPHDESCHI 0E0Eh
Key SAPHKEY 0E10h
Physical Interface Output Control #0 SAPHOCTL0 0E12h
Physical Interface Output Control #1 SAPHOCTL1 0E14h
Physical Interface Output Function Select SAPHOSEL 0E16h
Channel 0 Pull UpTrim SAPHCH0PUT 0E20h
Channel 0 Pull DownTrim SAPHCH0PDT 0E22h
Channel 0 Termination Trim SAPHCH0TT 0E24h
Channel 1 Pull UpTrim SAPHCH1PUT 0E26h
Channel 1 Pull DownTrim SAPHCH1PDT 0E28h
Channel 1 Termination Trim SAPHCH1TT 0E2Ah
Mode Configuration Register SAPHMCNF 0E2Ch
Trim Access Control SAPHTACTL 0E2Eh
Physical Interface Input Control #0 SAPHICTL0 0E30h
Bias Control SAPHBCTL 0E34h
PPG Count SAPHPGC 0E40h
Pulse Generator Low Period SAPHPGLPER 0E42h
Pulse Generator High Period SAPHPGHPER 0E44h
PPG Control SAPHPGCTL 0E46h
PPG Software Trigger SAPHPPGTRIG 0E48h
A-SEQ control 0 SAPHASCTL0 0E60h
A-SEQ control 1 SAPHASCTL1 0E62h
ASQ Software Trigger SAPHASQTRIG 0E64h
ASQ ping output polarity SAPHAPOL 0E66h
ASQ ping pause level SAPHAPLEV 0E68h
ASQ ping pause impedance SAPHAPHIZ 0E6Ah
A-SEQ start to 1st ping SAPHATM_A 0E6Eh
ASQ start to ADC arm SAPHATM_B 0E70h
Count for the TIMEMARK C Event SAPHATM_C 0E72h
ASQ start to ADC trig SAPHATM_D 0E74h
ASQ start to restart SAPHATM_E 0E76h
ASQ start to time-out SAPHATM_F 0E78h
Time Base Control SAPHTBCTL 0E7Ah
Acquisition Timer Low Part SAPHATIMLO 0E7Ch
Acquisition Timer High Part SAPHATIMHI 0E7Eh

Table 6-82 SDHS Registers(1)

REGISTER DESCRIPTION ACRONYM ADDRESS
Interrupt Index Register SDHSIIDX 0E80h
Masked Interrupt Status and Clear Register SDHSMIS 0E82h
Raw Interrupt Status SDHSRIS 0E84h
Interrupt Mask Register SDHSIMSC 0E86h
Interrupt Clear SDHSICR 0E88h
Interrupt Set Register SDHSISR 0E8Ah
SDHS Descriptor Register L SDHSDESCLO 0E8Ch
SDHS Descriptor Register H SDHSDESCHI 0E8Eh
SDHS Control Register 0 SDHSCTL0 0E90h
SDHS Control Register 1 SDHSCTL1 0E92h
SDHS Control Register 2 SDHSCTL2 0E94h
SDHS Control Register 3 SDHSCTL3 0E96h
SDHS Control Register 4 SDHSCTL4 0E98h
SDHS Control Register 5 SDHSCTL5 0E9Ah
SDHS Control Register 6 SDHSCTL6 0E9Ch
SDHS Control Register 7 SDHSCTL7 0E9Eh
SDHS Data Converstion Register SDHSDT 0EA2h
SDHS Window Comparator High Threshold Register SDHSWINHITH 0EA4h
SDHS Window Comparator Low Threshold Register SDHSWINLOTH 0EA6h
DTC destination address SDHSDTCDA 0EA8h
(1) Not available in MSP430FR6037, MSP430FR6035, and MSP430FR60371

Table 6-83 UUPS Registers(1)

REGISTER DESCRIPTION ACRONYM ADDRESS
Interrupt Index Register UUPSIIDX 0EC0h
Masked Interrupt Status UUPSMIS 0EC2h
Raw Interrupt Status UUPSRIS 0EC4h
Interrupt Mask Register UUPSIMSC 0EC6h
Interrupt Clear UUPSICR 0EC8h
Interrupt Flag Set UUPSISR 0ECAh
UUPS Descriptor Register L UUPSDESCLO 0ECCh
UUPS Descriptor Register H UUPSDESCHI 0ECEh
UUPS Control UUPSCTL 0ED0h
(1) Not available in MSP430FR6037, MSP430FR6035, and MSP430FR60371

Table 6-84 HSPLL Registers(1)

REGISTER DESCRIPTION ACRONYM ADDRESS
Interrupt Index Register HSPLLIIDX 0EE0h
Masked Interrupt Status HSPLLMIS 0EE2h
Raw Interrupt Status HSPLLRIS 0EE4h
Interrupt Mask Register HSPLLIMSC 0EE6h
Interrupt Flag Clear HSPLLICR 0EE8h
Interrupt Flag Set HSPLLISR 0EEAh
HSPLL Descriptor Register L HSPLLDESCLO 0EECh
HSPLL Descriptor Register H HSPLLDESCHI 0EEEh
HSPLL Control Register HSPLLCTL 0EF0h
USSXT Control Register HSPLLUSSXTLCTL 0EF2h
(1) Not available in MSP430FR6037, MSP430FR6035, and MSP430FR60371

Table 6-85 MTIF Registers

REGISTER DESCRIPTION ACRONYM ADDRESS
Pulse Generator Configuration MTIFPGCNF 0F00h
Pulse Generator Value MTIFPGKVAL 0F02h
Pulse Generator Control MTIFPGCTL 0F04h
Pulse Generator Status MTIFPGSR 0F06h
Pulse Counter Configuration MTIFPCCNF 0F08h
Pulse Counter Value MTIFPCR 0F0Ah
Pulse Counter Control MTIFPCCTL 0F0Ch
Pulse Counter Status MTIFPCSR 0F0Eh
Measurement Test Port Control MTIFTPCTL 0F10h
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