ZHCSGO9C June   2017  – September 2018 MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 5.11 Typical Characteristics, Current Consumption per Module
    12. 5.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.13.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.13.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.13.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charges
        3. 5.13.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.13.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.13.5.1   Typical Characteristics, Digital Outputs
      6. 5.13.6  LEA
        1. Table 5-13 Low-Energy Accelerator (LEA) Performance
      7. 5.13.7  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      8. 5.13.8  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-20 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-21 eUSCI (I2C Mode) Switching Characteristics
      9. 5.13.9  Segment LCD Controller
        1. Table 5-22 LCD_C Recommended Operating Conditions
        2. Table 5-23 LCD_C Electrical Characteristics
      10. 5.13.10 ADC12_B
        1. Table 5-24 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-25 12-Bit ADC, Timing Parameters
        3. Table 5-26 12-Bit ADC, Linearity Parameters
        4. Table 5-27 12-Bit ADC, Dynamic Performance With External Reference
        5. Table 5-28 12-Bit ADC, Dynamic Performance With Internal Reference
        6. Table 5-29 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. Table 5-30 12-Bit ADC, External Reference
      11. 5.13.11 Reference
        1. Table 5-31 REF, Built-In Reference
      12. 5.13.12 Comparator
        1. Table 5-32 Comparator_E
      13. 5.13.13 FRAM
        1. Table 5-33 FRAM
      14. 5.13.14 USS
        1. Table 5-34 USS Recommended Operating Conditions
        2. Table 5-35 USS LDO
        3. Table 5-36 USSXTAL
        4. Table 5-37 USS HSPLL
        5. Table 5-38 USS SDHS
        6. Table 5-39 USS PHY Output Stage
        7. Table 5-40 USS PHY Input Stage, Multiplexer
        8. Table 5-41 USS PGA
        9. Table 5-42 USS Bias Voltage Generator
      15. 5.13.15 Emulation and Debug
        1. Table 5-43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Ultrasonic Sensing Solution (USS) Module
    4. 6.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 6.5  Operating Modes
      1. 6.5.1 Peripherals in Low-Power Modes
      2. 6.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 6.6  Interrupt Vector Table and Signatures
    7. 6.7  Bootloader (BSL)
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire (SBW) Interface
    9. 6.9  FRAM Controller A (FRCTL_A)
    10. 6.10 RAM
    11. 6.11 Tiny RAM
    12. 6.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 6.13 Peripherals
      1. 6.13.1  Digital I/O
      2. 6.13.2  Oscillator and Clock System (CS)
      3. 6.13.3  Power-Management Module (PMM)
      4. 6.13.4  Hardware Multiplier (MPY)
      5. 6.13.5  Real-Time Clock (RTC_C)
      6. 6.13.6  Measurement Test Interface (MTIF)
      7. 6.13.7  Watchdog Timer (WDT_A)
      8. 6.13.8  System Module (SYS)
      9. 6.13.9  DMA Controller
      10. 6.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
      11. 6.13.11 TA0, TA1, and TA4
      12. 6.13.12 TA2 and TA3
      13. 6.13.13 TB0
      14. 6.13.14 ADC12_B
      15. 6.13.15 USS
      16. 6.13.16 Comparator_E
      17. 6.13.17 CRC16
      18. 6.13.18 CRC32
      19. 6.13.19 AES256 Accelerator
      20. 6.13.20 True Random Seed
      21. 6.13.21 Shared Reference (REF)
      22. 6.13.22 LCD_C
      23. 6.13.23 Embedded Emulation
        1. 6.13.23.1 Embedded Emulation Module (EEM) (S Version)
        2. 6.13.23.2 EnergyTrace++ Technology
    14. 6.14 Input/Output Diagrams
      1. 6.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 6.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 6.14.3  Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      4. 6.14.4  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      5. 6.14.5  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      6. 6.14.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      7. 6.14.7  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      8. 6.14.8  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      9. 6.14.9  Port P6 (P6.0) Input/Output With Schmitt Trigger
      10. 6.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 6.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      12. 6.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      13. 6.14.13 Port P7 (P7.4) Input/Output With Schmitt Trigger
      14. 6.14.14 Port P7 (P7.5) Input/Output With Schmitt Trigger
      15. 6.14.15 Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger
      16. 6.14.16 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      17. 6.14.17 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
      18. 6.14.18 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
      19. 6.14.19 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      20. 6.14.20 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      21. 6.14.21 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 6.15 Device Descriptors (TLV)
    16. 6.16 Memory Map
      1. 6.16.1 Peripheral File Map
    17. 6.17 Identification
      1. 6.17.1 Revision Identification
      2. 6.17.2 Device Identification
      3. 6.17.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1  Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2  External Oscillator (HFXT and LFXT)
      3. 7.1.3  USS Oscillator (USSXT)
      4. 7.1.4  Transducer Connection to the USS Module
      5. 7.1.5  Charge Pump Control of Input Multiplexer
      6. 7.1.6  JTAG
      7. 7.1.7  Reset
      8. 7.1.8  Unused Pins
      9. 7.1.9  General Layout Recommendations
      10. 7.1.10 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
      2. 7.2.2 LCD_C Peripheral
        1. 7.2.2.1 Partial Schematic
        2. 7.2.2.2 Design Requirements
        3. 7.2.2.3 Detailed Design Procedure
        4. 7.2.2.4 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1 入门和下一步
    2. 8.2 器件命名规则
    3. 8.3 工具和软件
    4. 8.4 文档支持
    5. 8.5 相关链接
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息

8.2 器件命名规则

为了标示米6体育平台手机版_好二三四开发周期所处的阶段，TI 为所有 MSP MCU 器件的部件号分配了前缀。每个 MSP MCU 商用系列米6体育平台手机版_好二三四成员都具有以下两个前缀之一：MSP 或 XMS。这些前缀代表了米6体育平台手机版_好二三四开发的发展阶段，即从工程原型 (XMS) 直到完全合格的生产器件 (MSP)。

XMS - 实验器件，不一定代表最终器件的电气规格

MSP - 完全合格的生产器件

XMS 器件在供货时附带如下免责声明：

“开发中的米6体育平台手机版_好二三四用于内部评估用途。”

MSP 器件的特性已经全部明确，并且器件的质量和可靠性已经完全论证。TI 的标准保修证书对该器件适用。

预测显示原型器件 (XMS) 的故障率大于标准生产器件。由于这些器件的预计最终使用故障率尚不确定，米6体育平台手机版_好二三四 (TI) 建议不要将它们用于任何生产系统。请仅使用合格的生产器件。

TI 器件的命名规则还包括一个带有器件系列名称的后缀。此后缀表示温度范围、封装类型和配送形式。Figure 8-1 提供了解读完整器件名称的图例。

MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371 MSP430FR6035 part_number_decoder_fr6047.gifFigure 8-1 器件命名规则
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