ZHCSGP5C August 2017 – February 2022 TIC12400-Q1
PRODUCTION DATA
The Read/Write bit (bit 31) of the SI bus needs to be set to logic 0 for a READ operation. The 6-bits address of the register to be accessed follows next on the SI bus. The content from bit 24 to bit 1 does not represent a valid command for a read operation and will be ignored. The LSB (bit 0) is the parity bit used to detect communication errors.
On the SO bus, the status flags will be outputted from the TIC12400-Q1, followed by the data content in the register that was requested. The LSB is the parity bit used to detect communication errors.
Note there are several test mode registers used in the TIC12400-Q1 in addition to the normal functional registers, and a READ command to these test registers returns the register content. If a READ command is issued to an invalid register address, the TIC12400-Q1 returns all 0s.