During normal operation of a typical 12 V automotive system, the V_S voltage is usually quite stable and stays well above 11 V. However, the V_S voltage may drop temporarily during certain vehicle operations, such as cold cranking. If the V_S voltage drops below V_{UV_F}, the TIC12400-Q1 enters the under-voltage (UV) condition since there is not enough voltage headroom for the device to accurately generate wetting currents. The following describes the behavior of the TIC12400-Q1 under UV condition:

1. All current sources and sinks de-activate and switch monitoring stops.
2. Interrupt is generated by asserting the INT pin low and the bit UV in the interrupt register (INT_STAT) is flagged to logic 1. The bit UV_STAT is asserted to logic 1 in the register IN_STAT_MISC. The OI SPI flag is asserted during any SPI transactions. The INT pin is released and the interrupt register (INT_STAT) is cleared on the rising edge of CS provided that the interrupt register has been read during the SPI transaction.
3. SPI communication stays active, and all register settings stay intact without resetting. Previous switch status, if needed, can be retrieved without interruption.
4. The device continues to monitor the V_S voltage, and the UV condition sustains if the V_S voltage continues to stay below V_{UV_R}. No further interrupt is generated once cleared.

Note: the device resets as described in section VS Supply POR if the V_S voltage drops below V_{POR_F}.

When the V_S voltage rises above V_{UV_R}, the INT pin is asserted low to notify the microcontroller that the UV condition no longer exists. The UV bit in the register INT_STAT is flagged to logic 1 and the bit UV_STAT bit is de-asserted to logic 0 in the register IN_STAT_MISC to reflect the clearance of the UV condition. The device resumes operation using current register settings (regardless of the INT pin and SPI communication status) with polling restarted from the first enabled channel. The Switch State Change (SSC) interrupt is generated at the end of the first polling cycle and the detected switch status becomes the baseline switch status for subsequent polling cycles. The content of the INT_STAT register, once read by the microcontroller, is cleared, and the INT pin is released afterwards.

The following diagram describes the TIC12400-Q1 operation at various different V_S voltages. If the V_S voltage stays above V_{UV_F} (Case 1), the device stays in normal operation. If the V_S voltage drops below V_{UV_F} but stays above V_{POR_F} (Case 2), the device enters the UV condition. If V_S voltage drops below V_{POR_F} (Case 3), the device resets and all register settings are cleared. The microcontroller is then required to re-program all the configuration registers in order to resume normal operation after the V_S voltage recovers.

Figure 8-2 TIC12400-Q1 Operation at Various V_S Voltage Levels