The system microcontroller selects the TIC10024-Q1 to receive communication using the CS pin. With the CS pin in a logic LOW state, command words may be sent to the TIC10024-Q1 through the serial input (SI) pin, and the device information can be retrieved by the microcontroller through the serial output (SO) pin. The falling edge of the CS enables the SO output and latches the content of the interrupt register INT_STAT. The microcontroller may issue a READ command to retrieve information stored in the registers. Rising edge on the CS pin initiates the following operations:

1. Disable the output driver and makes SO high-impedance.
2. INT pin is reset to logic HIGH if a READ command to the INT_STAT register was issued during CS = LOW.

To avoid corrupted data, it is essential the HIGH-to-LOW and LOW-to-HIGH transitions of the CS signal occur only when SCLK is in a logic LOW state. A clean CS signal is needed to ensure that no incomplete SPI words are sent to the device. The CS pin should be externally pulled up to VDD by a 10 kΩ resistor.