ZHCSGQ7C September 2017 – May 2019 TDP142
PRODUCTION DATA.
The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 2 details the gain value for each available combination when TDP142 is in GPIO mode. The I2C mode can do the same option or even individual lane EQ setting by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, and DP3EQ_SEL.
| Equalization Setting # | ALL DISPLAYPORT LANES | ||
|---|---|---|---|
| DPEQ1 PIN LEVEL | DPEQ0 PIN LEVEL | EQ GAIN at 4.05 GHz (dB) | |
| 0 | 0 | 0 | 1.0 |
| 1 | 0 | R | 3.3 |
| 2 | 0 | F | 4.9 |
| 3 | 0 | 1 | 6.5 |
| 4 | R | 0 | 7.5 |
| 5 | R | R | 8.6 |
| 6 | R | F | 9.5 |
| 7 | R | 1 | 10.4 |
| 8 | F | 0 | 11.1 |
| 9 | F | R | 11.7 |
| 10 | F | F | 12.3 |
| 11 | F | 1 | 12.8 |
| 12 | 1 | 0 | 13.2 |
| 13 | 1 | R | 13.6 |
| 14 | 1 | F | 14.0 |
| 15 | 1 | 1 | 14.4 |