ZHCSGQ7C September 2017 – May 2019 TDP142
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1 General Register (address = 0x0A) [reset = 00000001]
- 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
- 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
- 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
- 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
9.2.1 Source Application Implementation
Figure 18 shows the schematic for the Source side application. The TDP142 is placed between the DisplayPort Graphics Processor Unit (GPU) and the DisplayPort receptacle. The TDP142 monitors AUX traffic for power management purposes when SNOOPENZ is low.
Figure 18. The Block Diagram of DisplayPort Source Application