11.1 Layout Guidelines

1. INDP[3:0]P/N and OUTDP[3:0]P/N pairs should be routed with controlled 100-Ω differential impedance (±10%).
2. Keep away from other high speed signals.
3. Intra-pair routing should be kept to within 5 mils.
4. Inter-pair skew should be kept within 2 UI according to the DisaplyPort Design Guide
5. Length matching should be near the location of mismatch.
6. Each pair should be separated at least by 3 times the signal trace width.
7. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on EMI.
8. Route all differential pairs on the same of layer.
9. The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
10. Refer to figure 28, the layout might face signal crossing on OUTDP2 and OUTDP3 due to mismatched order between the output pins of the device and the connector. One of the solutions is to do polarity swap on the input of the device when GPU is BGA package. It can minimize the number of VIAS being used.
11. Keep traces on layers adjacent to ground plane.
12. Do NOT route differential pairs over any plane split.
13. Adding Test points will cause impedance discontinuity, and therefore, negatively impact signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair.