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Table 6-62 Switching Characteristics for McBSP0 [1.0V]⁽¹⁾⁽²⁾
(see Figure 6-34)

NO.	PARAMETER			1.0V		UNIT
NO.	PARAMETER			MIN	MAX	UNIT
1	t_{d(CKSH-CKRXH)}	Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input		3	21.5	ns
2	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X int	2P or 26.6⁽³⁾⁽³⁾⁽⁴⁾		ns
3	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X int	C - 2⁽⁵⁾	C + 2⁽⁵⁾	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR int	-4	10	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR ext	2.5	21.5	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX int	-4	10	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX ext	2.5	21.5	ns
12	t_{dis(CKXH-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX high	CLKX int	-4	10	ns
12	t_{dis(CKXH-DXHZ)}		CLKX ext	-2	21.5	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX int	-4 + D1⁽⁶⁾	10 + D2⁽⁶⁾	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX ext	2.5 + D1⁽⁶⁾	21.5 + D2⁽⁶⁾	ns
14	t_d(FXH-DXV)	Delay time, FSX high to DX valid	FSX int	-4⁽⁷⁾	5⁽⁷⁾	ns
14	t_d(FXH-DXV)	ONLY applies when in data delay 0 (XDATDLY = 00b) mode	FSX ext	-2⁽⁷⁾	21.5⁽⁷⁾	ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) Minimum delay times also represent minimum output hold times.

(3) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.

(4) Use whichever value is greater.

(5) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).

(6) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P

(7) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P

Table 6-62 Switching Characteristics for McBSP0 [1.0V](1)(2) (see Figure 6-34)

Table 6-62 Switching Characteristics for McBSP0 [1.0V]⁽¹⁾⁽²⁾
(see Figure 6-34)