ZHCSGV2J June   2009  – January 2017 OMAP-L138

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 DSP Subsystem
      1. 3.4.1 C674x DSP CPU Description
      2. 3.4.2 DSP Memory Mapping
        1. 3.4.2.1 ARM Internal Memories
        2. 3.4.2.2 External Memories
        3. 3.4.2.3 DSP Internal Memories
        4. 3.4.2.4 C674x CPU
    5. 3.5 Memory Map Summary
      1. Table 3-4 Top Level Memory Map
    6. 3.6 Pin Assignments
      1. 3.6.1 Pin Map (Bottom View)
    7. 3.7 Pin Multiplexing Control
    8. 3.8 Terminal Functions
      1. 3.8.1  Device Reset, NMI and JTAG
      2. 3.8.2  High-Frequency Oscillator and PLL
      3. 3.8.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.8.4  DEEPSLEEP Power Control
      5. 3.8.5  External Memory Interface A (EMIFA)
      6. 3.8.6  DDR2/mDDR Controller
      7. 3.8.7  Serial Peripheral Interface Modules (SPI)
      8. 3.8.8  Programmable Real-Time Unit (PRU)
      9. 3.8.9  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      10. 3.8.10 Enhanced Pulse Width Modulators (eHRPWM)
      11. 3.8.11 Boot
      12. 3.8.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      13. 3.8.13 Inter-Integrated Circuit Modules(I2C0, I2C1)
      14. 3.8.14 Timers
      15. 3.8.15 Multichannel Audio Serial Ports (McASP)
      16. 3.8.16 Multichannel Buffered Serial Ports (McBSP)
      17. 3.8.17 Universal Serial Bus Modules (USB0, USB1)
      18. 3.8.18 Ethernet Media Access Controller (EMAC)
      19. 3.8.19 Multimedia Card/Secure Digital (MMC/SD)
      20. 3.8.20 Liquid Crystal Display Controller(LCD)
      21. 3.8.21 Serial ATA Controller (SATA)
      22. 3.8.22 Universal Host-Port Interface (UHPI)
      23. 3.8.23 Universal Parallel Port (uPP)
      24. 3.8.24 Video Port Interface (VPIF)
      25. 3.8.25 General Purpose Input Output
      26. 3.8.26 Reserved and No Connect
      27. 3.8.27 Supply and Ground
    9. 3.9 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 ARM CPU Interrupts
        1. 6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 6.7.1.2 AINTC Hardware Vector Generation
        3. 6.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 6.7.1.4 AINTC System Interrupt Assignments
        5. 6.7.1.5 AINTC Memory Map
      2. 6.7.2 DSP Interrupts
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. 6.8.1.1 Power Domain States
        2. 6.8.1.2 Module States
    9. 6.9  Enhanced Direct Memory Access Controller (EDMA3)
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA3 Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface Register Descriptions
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-21 Timing Requirements for EMIFA SDRAM Interface
        2. Table 6-22 Switching Characteristics for EMIFA SDRAM Interface
        3. Table 6-23 Timing Requirements for EMIFA Asynchronous Memory Interface
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Memory Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1. 6.11.3.1  DDR2/mDDR Interface Schematic
        2. 6.11.3.2  Compatible JEDEC DDR2/mDDR Devices
        3. 6.11.3.3  PCB Stackup
        4. 6.11.3.4  Placement
        5. 6.11.3.5  DDR2/mDDR Keep Out Region
        6. 6.11.3.6  Bulk Bypass Capacitors
        7. 6.11.3.7  High-Speed Bypass Capacitors
        8. 6.11.3.8  Net Classes
        9. 6.11.3.9  DDR2/mDDR Signal Termination
        10. 6.11.3.10 VREF Routing
        11. 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
        12. 6.11.3.12 DDR2/mDDR Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
        1. Table 6-42 Timing Requirements for MMC/SD (see and )
        2. Table 6-43 Switching Characteristics for MMC/SD (see through )
    14. 6.14 Serial ATA Controller (SATA)
      1. 6.14.1 SATA Register Descriptions
      2. 6.14.2 1. SATA Interface
        1. 6.14.2.1 SATA Interface Schematic
        2. 6.14.2.2 Compatible SATA Components and Modes
        3. 6.14.2.3 PCB Stackup Specifications
        4. 6.14.2.4 Routing Specifications
        5. 6.14.2.5 Coupling Capacitors
        6. 6.14.2.6 SATA Interface Clock Source requirements
      3. 6.14.3 SATA Unused Signal Configuration
    15. 6.15 Multichannel Audio Serial Port (McASP)
      1. 6.15.1 McASP Peripheral Registers Description(s)
      2. 6.15.2 McASP Electrical Data/Timing
        1. 6.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-54 Timing Requirements for McASP0 (1.3V, 1.2V, 1.1V)
          2. Table 6-55 Timing Requirements for McASP0 (1.0V)
          3. Table 6-56 Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)
          4. Table 6-57 Switching Characteristics for McASP0 (1.0V)
    16. 6.16 Multichannel Buffered Serial Port (McBSP)
      1. 6.16.1 McBSP Peripheral Register Description(s)
      2. 6.16.2 McBSP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Buffered Serial Port (McBSP) Timing
          1. Table 6-59 Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V] (see )
          2. Table 6-60 Timing Requirements for McBSP0 [1.0V] (see )
          3. Table 6-61 Switching Characteristics for McBSP0 [1.3V, 1.2V, 1.1V] (see )
          4. Table 6-62 Switching Characteristics for McBSP0 [1.0V] (see )
          5. Table 6-63 Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V] (see )
          6. Table 6-64 Timing Requirements for McBSP1 [1.0V] (see )
          7. Table 6-65 Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V] (see )
          8. Table 6-66 Switching Characteristics for McBSP1 [1.0V] (see )
          9. Table 6-67 Timing Requirements for McBSP0 FSR When GSYNC = 1 (see )
          10. Table 6-68 Timing Requirements for McBSP1 FSR When GSYNC = 1 (see )
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-70 General Timing Requirements for SPI0 Master Modes
          2. Table 6-71 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-78 General Timing Requirements for SPI1 Master Modes
          4. Table 6-79 General Timing Requirements for SPI1 Slave Modes
          5. Table 6-80 Additional SPI1 Master Timings, 4-Pin Enable Option
          6. Table 6-81 Additional SPI1 Master Timings, 4-Pin Chip Select Option
    18. 6.18 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.18.1 I2C Device-Specific Information
      2. 6.18.2 I2C Peripheral Registers Description(s)
      3. 6.18.3 I2C Electrical Data/Timing
        1. 6.18.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-87 Timing Requirements for I2C Input
          2. Table 6-88 Switching Characteristics for I2C
    19. 6.19 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.19.1 UART Peripheral Registers Description(s)
      2. 6.19.2 UART Electrical Data/Timing
        1. Table 6-90 Timing Requirements for UART Receive (see )
        2. Table 6-91 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    20. 6.20 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
      1. 6.20.1 USB0 [USB2.0] Electrical Data/Timing
        1. Table 6-93 Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see )
    21. 6.21 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]
      1. Table 6-95 Switching Characteristics Over Recommended Operating Conditions for USB1 [USB1.1]
    22. 6.22 Ethernet Media Access Controller (EMAC)
      1. 6.22.1 EMAC Peripheral Register Description(s)
        1. 6.22.1.1 EMAC Electrical Data/Timing
          1. Table 6-100 Timing Requirements for MII_RXCLK (see )
          2. Table 6-101 Timing Requirements for MII_TXCLK (see )
          3. Table 6-102 Timing Requirements for EMAC MII Receive 10/100 Mbit/s (see )
          4. Table 6-103 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s (see )
    23. 6.23 Management Data Input/Output (MDIO)
      1. 6.23.1 MDIO Register Description(s)
      2. 6.23.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-107 Timing Requirements for MDIO Input (see and )
        2. Table 6-108 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    24. 6.24 LCD Controller (LCDC)
      1. 6.24.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.24.2 LCD Raster Mode
        1. Table 6-112 Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode
    25. 6.25 Host-Port Interface (UHPI)
      1. 6.25.1 HPI Device-Specific Information
      2. 6.25.2 HPI Peripheral Register Description(s)
      3. 6.25.3 HPI Electrical Data/Timing
        1. Table 6-114 Timing Requirements for Host-Port Interface [1.2V, 1.1V]
        2. Table 6-115 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.3V, 1.2V, 1.1V]
        3. Table 6-116 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V]
    26. 6.26 Universal Parallel Port (uPP)
      1. 6.26.1 uPP Register Descriptions
        1. Table 6-117 Universal Parallel Port (uPP) Registers
      2. 6.26.2 uPP Electrical Data/Timing
        1. Table 6-118 Timing Requirements for uPP (see , , , )
        2. Table 6-119 Switching Characteristics Over Recommended Operating Conditions for uPP
    27. 6.27 Video Port Interface (VPIF)
      1. 6.27.1 VPIF Register Descriptions
        1. Table 6-120 Video Port Interface (VPIF) Registers
      2. 6.27.2 VPIF Electrical Data/Timing
        1. Table 6-121 Timing Requirements for VPIF VP_CLKINx Inputs (see )
        2. Table 6-122 Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs (see )
        3. Table 6-123 Switching Characteristics Over Recommended Operating Conditions for Video Data Shown With Respect to VP_CLKOUT2/3 (see )
    28. 6.28 Enhanced Capture (eCAP) Peripheral
      1. Table 6-125 Timing Requirements for Enhanced Capture (eCAP)
      2. Table 6-126 Switching Characteristics Over Recommended Operating Conditions for eCAP
    29. 6.29 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.29.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-128 Timing Requirements for eHRPWM
        2. Table 6-129 Switching Characteristics Over Recommended Operating Conditions for eHRPWM
      2. 6.29.2 Trip-Zone Input Timing
    30. 6.30 Timers
      1. 6.30.1 Timer Electrical Data/Timing
        1. Table 6-132 Timing Requirements for Timer Input (see )
        2. Table 6-133 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    31. 6.31 Real Time Clock (RTC)
      1. 6.31.1 Clock Source
      2. 6.31.2 Real-Time Clock Register Descriptions
    32. 6.32 General-Purpose Input/Output (GPIO)
      1. 6.32.1 GPIO Register Description(s)
      2. 6.32.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-136 Timing Requirements for GPIO Inputs (see )
        2. Table 6-137 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.32.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-138 Timing Requirements for External Interrupts (see )
    33. 6.33 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.33.1 PRUSS Register Descriptions
    34. 6.34 Emulation Logic
      1. 6.34.1 JTAG Port Description
      2. 6.34.2 Scan Chain Configuration Parameters
      3. 6.34.3 Initial Scan Chain Configuration
        1. 6.34.3.1 Adding TAPS to the Scan Chain
      4. 6.34.4 IEEE 1149.1 JTAG
        1. 6.34.4.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
        2. 6.34.4.2 JTAG Test-Port Electrical Data/Timing
          1. Table 6-150 Timing Requirements for JTAG Test Port (see )
          2. Table 6-151 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
      5. 6.34.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 社区资源
    5. 7.5 商标
    6. 7.6 静电放电警告
    7. 7.7 出口管制提示
    8. 7.8 术语表
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZCE Package
    2. 8.2 Thermal Data for ZWT Package
    3. 8.3 Packaging Information

3.4.2.4 C674x CPU

The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both.

Table 3-2 shows a memory map of the C674x CPU cache registers for the device.

Table 3-2 C674x Cache Registers

Byte Address Register Name Register Description
0x0184 0000 L2CFG L2 Cache configuration register
0x0184 0020 L1PCFG L1P Size Cache configuration register
0x0184 0024 L1PCC L1P Freeze Mode Cache configuration register
0x0184 0040 L1DCFG L1D Size Cache configuration register
0x0184 0044 L1DCC L1D Freeze Mode Cache configuration register
0x0184 0048 - 0x0184 0FFC - Reserved
0x0184 1000 EDMAWEIGHT L2 EDMA access control register
0x0184 1004 - 0x0184 1FFC - Reserved
0x0184 2000 L2ALLOC0 L2 allocation register 0
0x0184 2004 L2ALLOC1 L2 allocation register 1
0x0184 2008 L2ALLOC2 L2 allocation register 2
0x0184 200C L2ALLOC3 L2 allocation register 3
0x0184 2010 - 0x0184 3FFF - Reserved
0x0184 4000 L2WBAR L2 writeback base address register
0x0184 4004 L2WWC L2 writeback word count register
0x0184 4010 L2WIBAR L2 writeback invalidate base address register
0x0184 4014 L2WIWC L2 writeback invalidate word count register
0x0184 4018 L2IBAR L2 invalidate base address register
0x0184 401C L2IWC L2 invalidate word count register
0x0184 4020 L1PIBAR L1P invalidate base address register
0x0184 4024 L1PIWC L1P invalidate word count register
0x0184 4030 L1DWIBAR L1D writeback invalidate base address register
0x0184 4034 L1DWIWC L1D writeback invalidate word count register
0x0184 4038 - Reserved
0x0184 4040 L1DWBAR L1D Block Writeback
0x0184 4044 L1DWWC L1D Block Writeback
0x0184 4048 L1DIBAR L1D invalidate base address register
0x0184 404C L1DIWC L1D invalidate word count register
0x0184 4050 - 0x0184 4FFF - Reserved
0x0184 5000 L2WB L2 writeback all register
0x0184 5004 L2WBINV L2 writeback invalidate all register
0x0184 5008 L2INV L2 Global Invalidate without writeback
0x0184 500C - 0x0184 5027 - Reserved
0x0184 5028 L1PINV L1P Global Invalidate
0x0184 502C - 0x0184 5039 - Reserved
0x0184 5040 L1DWB L1D Global Writeback
0x0184 5044 L1DWBINV L1D Global Writeback with Invalidate
0x0184 5048 L1DINV L1D Global Invalidate without writeback
0x0184 8000 – 0x0184 80FF MAR0 - MAR63 Reserved 0x0000 0000 – 0x3FFF FFFF
0x0184 8100 – 0x0184 817F MAR64 – MAR95 Memory Attribute Registers for EMIFA SDRAM Data (CS0)
External memory addresses 0x4000 0000 – 0x5FFF FFFF
0x0184 8180 – 0x0184 8187 MAR96 - MAR97 Memory Attribute Registers for EMIFA Async Data (CS2)
External memory addresses 0x6000 0000 – 0x61FF FFFF
0x0184 8188 – 0x0184 818F MAR98 – MAR99 Memory Attribute Registers for EMIFA Async Data (CS3)
External memory addresses 0x6200 0000 – 0x63FF FFFF
0x0184 8190 – 0x0184 8197 MAR100 – MAR101 Memory Attribute Registers for EMIFA Async Data (CS4)
External memory addresses 0x6400 0000 – 0x65FF FFFF
0x0184 8198 – 0x0184 819F MAR102 – MAR103 Memory Attribute Registers for EMIFA Async Data (CS5)
External memory addresses 0x6600 0000 – 0x67FF FFFF
0x0184 81A0 – 0x0184 81FF MAR104 – MAR127 Reserved 0x6800 0000 – 0x7FFF FFFF
0x0184 8200 MAR128 Memory Attribute Register for Shared RAM
External memory addresses 0x8000 0000 – 0x8001 FFFF
Reserved 0x8002 0000 – 0x81FF FFFF
0x0184 8204 – 0x0184 82FF MAR129 – MAR191 Reserved 0x8200 0000 – 0xBFFF FFFF
0x0184 8300 – 0x0184 837F MAR192 – MAR223 Memory Attribute Registers for DDR2 Data (CS2)
External memory addresses 0xC000 0000 – 0xDFFF FFFF
0x0184 8380 – 0x0184 83FF MAR224 – MAR255 Reserved 0xE000 0000 – 0xFFFF FFFF

Table 3-3 C674x L1/L2 Memory Protection Registers

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION
0x0184 A000 L2MPFAR L2 memory protection fault address register
0x0184 A004 L2MPFSR L2 memory protection fault status register
0x0184 A008 L2MPFCR L2 memory protection fault command register
0x0184 A00C - 0x0184 A0FF - Reserved
0x0184 A100 L2MPLK0 L2 memory protection lock key bits [31:0]
0x0184 A104 L2MPLK1 L2 memory protection lock key bits [63:32]
0x0184 A108 L2MPLK2 L2 memory protection lock key bits [95:64]
0x0184 A10C L2MPLK3 L2 memory protection lock key bits [127:96]
0x0184 A110 L2MPLKCMD L2 memory protection lock key command register
0x0184 A114 L2MPLKSTAT L2 memory protection lock key status register
0x0184 A118 - 0x0184 A1FF - Reserved
0x0184 A200 L2MPPA0 L2 memory protection page attribute register 0 (controls memory address 0x0080 0000 - 0x0080 1FFF)
0x0184 A204 L2MPPA1 L2 memory protection page attribute register 1 (controls memory address 0x0080 2000 - 0x0080 3FFF)
0x0184 A208 L2MPPA2 L2 memory protection page attribute register 2 (controls memory address 0x0080 4000 - 0x0080 5FFF)
0x0184 A20C L2MPPA3 L2 memory protection page attribute register 3 (controls memory address 0x0080 6000 - 0x0080 7FFF)
0x0184 A210 L2MPPA4 L2 memory protection page attribute register 4 (controls memory address 0x0080 8000 - 0x0080 9FFF)
0x0184 A214 L2MPPA5 L2 memory protection page attribute register 5 (controls memory address 0x0080 A000 - 0x0080 BFFF)
0x0184 A218 L2MPPA6 L2 memory protection page attribute register 6 (controls memory address 0x0080 C000 - 0x0080 DFFF)
0x0184 A21C L2MPPA7 L2 memory protection page attribute register 7 (controls memory address 0x0080 E000 - 0x0080 FFFF)
0x0184 A220 L2MPPA8 L2 memory protection page attribute register 8 (controls memory address 0x0081 0000 - 0x0081 1FFF)
0x0184 A224 L2MPPA9 L2 memory protection page attribute register 9 (controls memory address 0x0081 2000 - 0x0081 3FFF)
0x0184 A228 L2MPPA10 L2 memory protection page attribute register 10 (controls memory address 0x0081 4000 - 0x0081 5FFF)
0x0184 A22C L2MPPA11 L2 memory protection page attribute register 11 (controls memory address 0x0081 6000 - 0x0081 7FFF)
0x0184 A230 L2MPPA12 L2 memory protection page attribute register 12 (controls memory address 0x0081 8000 - 0x0081 9FFF)
0x0184 A234 L2MPPA13 L2 memory protection page attribute register 13 (controls memory address 0x0081 A000 - 0x0081 BFFF)
0x0184 A238 L2MPPA14 L2 memory protection page attribute register 14 (controls memory address 0x0081 C000 - 0x0081 DFFF)
0x0184 A23C L2MPPA15 L2 memory protection page attribute register 15 (controls memory address 0x0081 E000 - 0x0081 FFFF)
0x0184 A240 L2MPPA16 L2 memory protection page attribute register 16 (controls memory address 0x0082 0000 - 0x0082 1FFF)
0x0184 A244 L2MPPA17 L2 memory protection page attribute register 17 (controls memory address 0x0082 2000 - 0x0082 3FFF)
0x0184 A248 L2MPPA18 L2 memory protection page attribute register 18 (controls memory address 0x0082 4000 - 0x0082 5FFF)
0x0184 A24C L2MPPA19 L2 memory protection page attribute register 19 (controls memory address 0x0082 6000 - 0x0082 7FFF)
0x0184 A250 L2MPPA20 L2 memory protection page attribute register 20 (controls memory address 0x0082 8000 - 0x0082 9FFF)
0x0184 A254 L2MPPA21 L2 memory protection page attribute register 21 (controls memory address 0x0082 A000 - 0x0082 BFFF)
0x0184 A258 L2MPPA22 L2 memory protection page attribute register 22 (controls memory address 0x0082 C000 - 0x0082 DFFF)
0x0184 A25C L2MPPA23 L2 memory protection page attribute register 23 (controls memory address 0x0082 E000 - 0x0082 FFFF)
0x0184 A260 L2MPPA24 L2 memory protection page attribute register 24 (controls memory address 0x0083 0000 - 0x0083 1FFF)
0x0184 A264 L2MPPA25 L2 memory protection page attribute register 25 (controls memory address 0x0083 2000 - 0x0083 3FFF)
0x0184 A268 L2MPPA26 L2 memory protection page attribute register 26 (controls memory address 0x0083 4000 - 0x0083 5FFF)
0x0184 A26C L2MPPA27 L2 memory protection page attribute register 27 (controls memory address 0x0083 6000 - 0x0083 7FFF)
0x0184 A270 L2MPPA28 L2 memory protection page attribute register 28 (controls memory address 0x0083 8000 - 0x0083 9FFF)
0x0184 A274 L2MPPA29 L2 memory protection page attribute register 29 (controls memory address 0x0083 A000 - 0x0083 BFFF)
0x0184 A278 L2MPPA30 L2 memory protection page attribute register 30 (controls memory address 0x0083 C000 - 0x0083 DFFF)
0x0184 A27C L2MPPA31 L2 memory protection page attribute register 31 (controls memory address 0x0083 E000 - 0x0083 FFFF)
0x0184 A280 L2MPPA32 L2 memory protection page attribute register 32 (controls memory address 0x0070 0000 - 0x0070 7FFF)
0x0184 A284 L2MPPA33 L2 memory protection page attribute register 33 (controls memory address 0x0070 8000 - 0x0070 FFFF)
0x0184 A288 L2MPPA34 L2 memory protection page attribute register 34 (controls memory address 0x0071 0000 - 0x0071 7FFF)
0x0184 A28C L2MPPA35 L2 memory protection page attribute register 35 (controls memory address 0x0071 8000 - 0x0071 FFFF)
0x0184 A290 L2MPPA36 L2 memory protection page attribute register 36 (controls memory address 0x0072 0000 - 0x0072 7FFF)
0x0184 A294 L2MPPA37 L2 memory protection page attribute register 37 (controls memory address 0x0072 8000 - 0x0072 FFFF)
0x0184 A298 L2MPPA38 L2 memory protection page attribute register 38 (controls memory address 0x0073 0000 - 0x0073 7FFF)
0x0184 A29C L2MPPA39 L2 memory protection page attribute register 39 (controls memory address 0x0073 8000 - 0x0073 FFFF)
0x0184 A2A0 L2MPPA40 L2 memory protection page attribute register 40 (controls memory address 0x0074 0000 - 0x0074 7FFF)
0x0184 A2A4 L2MPPA41 L2 memory protection page attribute register 41 (controls memory address 0x0074 8000 - 0x0074 FFFF)
0x0184 A2A8 L2MPPA42 L2 memory protection page attribute register 42 (controls memory address 0x0075 0000 - 0x0075 7FFF)
0x0184 A2AC L2MPPA43 L2 memory protection page attribute register 43 (controls memory address 0x0075 8000 - 0x0075 FFFF)
0x0184 A2B0 L2MPPA44 L2 memory protection page attribute register 44 (controls memory address 0x0076 0000 - 0x0076 7FFF)
0x0184 A2B4 L2MPPA45 L2 memory protection page attribute register 45 (controls memory address 0x0076 8000 - 0x0076 FFFF)
0x0184 A2B8 L2MPPA46 L2 memory protection page attribute register 46 (controls memory address 0x0077 0000 - 0x0077 7FFF)
0x0184 A2BC L2MPPA47 L2 memory protection page attribute register 47 (controls memory address 0x0077 8000 - 0x0077 FFFF)
0x0184 A2C0 L2MPPA48 L2 memory protection page attribute register 48 (controls memory address 0x0078 0000 - 0x0078 7FFF)
0x0184 A2C4 L2MPPA49 L2 memory protection page attribute register 49 (controls memory address 0x0078 8000 - 0x0078 FFFF)
0x0184 A2C8 L2MPPA50 L2 memory protection page attribute register 50 (controls memory address 0x0079 0000 - 0x0079 7FFF)
0x0184 A2CC L2MPPA51 L2 memory protection page attribute register 51 (controls memory address 0x0079 8000 - 0x0079 FFFF)
0x0184 A2D0 L2MPPA52 L2 memory protection page attribute register 52 (controls memory address 0x007A 0000 - 0x007A 7FFF)
0x0184 A2D4 L2MPPA53 L2 memory protection page attribute register 53 (controls memory address 0x007A 8000 - 0x007A FFFF)
0x0184 A2D8 L2MPPA54 L2 memory protection page attribute register 54 (controls memory address 0x007B 0000 - 0x007B 7FFF)
0x0184 A2DC L2MPPA55 L2 memory protection page attribute register 55 (controls memory address 0x007B 8000 - 0x007B FFFF)
0x0184 A2E0 L2MPPA56 L2 memory protection page attribute register 56 (controls memory address 0x007C 0000 - 0x007C 7FFF)
0x0184 A2E4 L2MPPA57 L2 memory protection page attribute register 57 (controls memory address 0x007C 8000 - 0x007C FFFF)
0x0184 A2E8 L2MPPA58 L2 memory protection page attribute register 58 (controls memory address 0x007D 0000 - 0x007D 7FFF)
0x0184 A2EC L2MPPA59 L2 memory protection page attribute register 59 (controls memory address 0x007D 8000 - 0x007D FFFF)
0x0184 A2F0 L2MPPA60 L2 memory protection page attribute register 60 (controls memory address 0x007E 0000 - 0x007E 7FFF)
0x0184 A2F4 L2MPPA61 L2 memory protection page attribute register 61 (controls memory address 0x007E 8000 - 0x007E FFFF)
0x0184 A2F8 L2MPPA62 L2 memory protection page attribute register 62 (controls memory address 0x007F 0000 - 0x007F 7FFF)
0x0184 A2FC L2MPPA63 L2 memory protection page attribute register 63 (controls memory address 0x007F 8000 - 0x007F FFFF)
0x0184 A300 - 0x0184 A3FF - Reserved
0x0184 A400 L1PMPFAR L1P memory protection fault address register
0x0184 A404 L1PMPFSR L1P memory protection fault status register
0x0184 A408 L1PMPFCR L1P memory protection fault command register
0x0184 A40C - 0x0184 A4FF - Reserved
0x0184 A500 L1PMPLK0 L1P memory protection lock key bits [31:0]
0x0184 A504 L1PMPLK1 L1P memory protection lock key bits [63:32]
0x0184 A508 L1PMPLK2 L1P memory protection lock key bits [95:64]
0x0184 A50C L1PMPLK3 L1P memory protection lock key bits [127:96]
0x0184 A510 L1PMPLKCMD L1P memory protection lock key command register
0x0184 A514 L1PMPLKSTAT L1P memory protection lock key status register
0x0184 A518 - 0x0184 A5FF - Reserved
0x0184 A600 - 0x0184 A63F - Reserved (1)
0x0184 A640 L1PMPPA16 L1P memory protection page attribute register 16 (controls memory address 0x00E0 0000 - 0x00E0 07FF)
0x0184 A644 L1PMPPA17 L1P memory protection page attribute register 17 (controls memory address 0x00E0 0800 - 0x00E0 0FFF)
0x0184 A648 L1PMPPA18 L1P memory protection page attribute register 18 (controls memory address 0x00E0 1000 - 0x00E0 17FF)
0x0184 A64C L1PMPPA19 L1P memory protection page attribute register 19 (controls memory address 0x00E0 1800 - 0x00E0 1FFF)
0x0184 A650 L1PMPPA20 L1P memory protection page attribute register 20 (controls memory address 0x00E0 2000 - 0x00E0 27FF)
0x0184 A654 L1PMPPA21 L1P memory protection page attribute register 21 (controls memory address 0x00E0 2800 - 0x00E0 2FFF)
0x0184 A658 L1PMPPA22 L1P memory protection page attribute register 22 (controls memory address 0x00E0 3000 - 0x00E0 37FF)
0x0184 A65C L1PMPPA23 L1P memory protection page attribute register 23 (controls memory address 0x00E0 3800 - 0x00E0 3FFF)
0x0184 A660 L1PMPPA24 L1P memory protection page attribute register 24 (controls memory address 0x00E0 4000 - 0x00E0 47FF)
0x0184 A664 L1PMPPA25 L1P memory protection page attribute register 25 (controls memory address 0x00E0 4800 - 0x00E0 4FFF)
0x0184 A668 L1PMPPA26 L1P memory protection page attribute register 26 (controls memory address 0x00E0 5000 - 0x00E0 57FF)
0x0184 A66C L1PMPPA27 L1P memory protection page attribute register 27 (controls memory address 0x00E0 5800 - 0x00E0 5FFF)
0x0184 A670 L1PMPPA28 L1P memory protection page attribute register 28 (controls memory address 0x00E0 6000 - 0x00E0 67FF)
0x0184 A674 L1PMPPA29 L1P memory protection page attribute register 29 (controls memory address 0x00E0 6800 - 0x00E0 6FFF)
0x0184 A678 L1PMPPA30 L1P memory protection page attribute register 30 (controls memory address 0x00E0 7000 - 0x00E0 77FF)
0x0184 A67C L1PMPPA31 L1P memory protection page attribute register 31 (controls memory address 0x00E0 7800 - 0x00E0 7FFF)
0x0184 A67F – 0x0184 ABFF - Reserved
0x0184 AC00 L1DMPFAR L1D memory protection fault address register
0x0184 AC04 L1DMPFSR L1D memory protection fault status register
0x0184 AC08 L1DMPFCR L1D memory protection fault command register
0x0184 AC0C - 0x0184 ACFF - Reserved
0x0184 AD00 L1DMPLK0 L1D memory protection lock key bits [31:0]
0x0184 AD04 L1DMPLK1 L1D memory protection lock key bits [63:32]
0x0184 AD08 L1DMPLK2 L1D memory protection lock key bits [95:64]
0x0184 AD0C L1DMPLK3 L1D memory protection lock key bits [127:96]
0x0184 AD10 L1DMPLKCMD L1D memory protection lock key command register
0x0184 AD14 L1DMPLKSTAT L1D memory protection lock key status register
0x0184 AD18 - 0x0184 ADFF - Reserved
0x0184 AE00 - 0x0184 AE3F - Reserved (2)
0x0184 AE40 L1DMPPA16 L1D memory protection page attribute register 16 (controls memory address 0x00F0 0000 - 0x00F0 07FF)
0x0184 AE44 L1DMPPA17 L1D memory protection page attribute register 17 (controls memory address 0x00F0 0800 - 0x00F0 0FFF)
0x0184 AE48 L1DMPPA18 L1D memory protection page attribute register 18 (controls memory address 0x00F0 1000 - 0x00F0 17FF)
0x0184 AE4C L1DMPPA19 L1D memory protection page attribute register 19 (controls memory address 0x00F0 1800 - 0x00F0 1FFF)
0x0184 AE50 L1DMPPA20 L1D memory protection page attribute register 20 (controls memory address 0x00F0 2000 - 0x00F0 27FF)
0x0184 AE54 L1DMPPA21 L1D memory protection page attribute register 21 (controls memory address 0x00F0 2800 - 0x00F0 2FFF)
0x0184 AE58 L1DMPPA22 L1D memory protection page attribute register 22 (controls memory address 0x00F0 3000 - 0x00F0 37FF)
0x0184 AE5C L1DMPPA23 L1D memory protection page attribute register 23 (controls memory address 0x00F0 3800 - 0x00F0 3FFF)
0x0184 AE60 L1DMPPA24 L1D memory protection page attribute register 24 (controls memory address 0x00F0 4000 - 0x00F0 47FF)
0x0184 AE64 L1DMPPA25 L1D memory protection page attribute register 25 (controls memory address 0x00F0 4800 - 0x00F0 4FFF)
0x0184 AE68 L1DMPPA26 L1D memory protection page attribute register 26 (controls memory address 0x00F0 5000 - 0x00F0 57FF)
0x0184 AE6C L1DMPPA27 L1D memory protection page attribute register 27 (controls memory address 0x00F0 5800 - 0x00F0 5FFF)
0x0184 AE70 L1DMPPA28 L1D memory protection page attribute register 28 (controls memory address 0x00F0 6000 - 0x00F0 67FF)
0x0184 AE74 L1DMPPA29 L1D memory protection page attribute register 29 (controls memory address 0x00F0 6800 - 0x00F0 6FFF)
0x0184 AE78 L1DMPPA30 L1D memory protection page attribute register 30 (controls memory address 0x00F0 7000 - 0x00F0 77FF)
0x0184 AE7C L1DMPPA31 L1D memory protection page attribute register 31 (controls memory address 0x00F0 7800 - 0x00F0 7FFF)
0x0184 AE80 – 0x0185 FFFF - Reserved
(1) These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0-L1PMPPA15) of the C674x megamaodule. These registers are not supported for this device.
(2) These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0-L1DMPPA15) of the C674x megamaodule. These registers are not supported for this device.
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