ZHCSGV2J June   2009  – January 2017 OMAP-L138

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 DSP Subsystem
      1. 3.4.1 C674x DSP CPU Description
      2. 3.4.2 DSP Memory Mapping
        1. 3.4.2.1 ARM Internal Memories
        2. 3.4.2.2 External Memories
        3. 3.4.2.3 DSP Internal Memories
        4. 3.4.2.4 C674x CPU
    5. 3.5 Memory Map Summary
      1. Table 3-4 Top Level Memory Map
    6. 3.6 Pin Assignments
      1. 3.6.1 Pin Map (Bottom View)
    7. 3.7 Pin Multiplexing Control
    8. 3.8 Terminal Functions
      1. 3.8.1  Device Reset, NMI and JTAG
      2. 3.8.2  High-Frequency Oscillator and PLL
      3. 3.8.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.8.4  DEEPSLEEP Power Control
      5. 3.8.5  External Memory Interface A (EMIFA)
      6. 3.8.6  DDR2/mDDR Controller
      7. 3.8.7  Serial Peripheral Interface Modules (SPI)
      8. 3.8.8  Programmable Real-Time Unit (PRU)
      9. 3.8.9  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      10. 3.8.10 Enhanced Pulse Width Modulators (eHRPWM)
      11. 3.8.11 Boot
      12. 3.8.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      13. 3.8.13 Inter-Integrated Circuit Modules(I2C0, I2C1)
      14. 3.8.14 Timers
      15. 3.8.15 Multichannel Audio Serial Ports (McASP)
      16. 3.8.16 Multichannel Buffered Serial Ports (McBSP)
      17. 3.8.17 Universal Serial Bus Modules (USB0, USB1)
      18. 3.8.18 Ethernet Media Access Controller (EMAC)
      19. 3.8.19 Multimedia Card/Secure Digital (MMC/SD)
      20. 3.8.20 Liquid Crystal Display Controller(LCD)
      21. 3.8.21 Serial ATA Controller (SATA)
      22. 3.8.22 Universal Host-Port Interface (UHPI)
      23. 3.8.23 Universal Parallel Port (uPP)
      24. 3.8.24 Video Port Interface (VPIF)
      25. 3.8.25 General Purpose Input Output
      26. 3.8.26 Reserved and No Connect
      27. 3.8.27 Supply and Ground
    9. 3.9 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 ARM CPU Interrupts
        1. 6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 6.7.1.2 AINTC Hardware Vector Generation
        3. 6.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 6.7.1.4 AINTC System Interrupt Assignments
        5. 6.7.1.5 AINTC Memory Map
      2. 6.7.2 DSP Interrupts
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. 6.8.1.1 Power Domain States
        2. 6.8.1.2 Module States
    9. 6.9  Enhanced Direct Memory Access Controller (EDMA3)
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA3 Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface Register Descriptions
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-21 Timing Requirements for EMIFA SDRAM Interface
        2. Table 6-22 Switching Characteristics for EMIFA SDRAM Interface
        3. Table 6-23 Timing Requirements for EMIFA Asynchronous Memory Interface
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Memory Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1. 6.11.3.1  DDR2/mDDR Interface Schematic
        2. 6.11.3.2  Compatible JEDEC DDR2/mDDR Devices
        3. 6.11.3.3  PCB Stackup
        4. 6.11.3.4  Placement
        5. 6.11.3.5  DDR2/mDDR Keep Out Region
        6. 6.11.3.6  Bulk Bypass Capacitors
        7. 6.11.3.7  High-Speed Bypass Capacitors
        8. 6.11.3.8  Net Classes
        9. 6.11.3.9  DDR2/mDDR Signal Termination
        10. 6.11.3.10 VREF Routing
        11. 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
        12. 6.11.3.12 DDR2/mDDR Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
        1. Table 6-42 Timing Requirements for MMC/SD (see and )
        2. Table 6-43 Switching Characteristics for MMC/SD (see through )
    14. 6.14 Serial ATA Controller (SATA)
      1. 6.14.1 SATA Register Descriptions
      2. 6.14.2 1. SATA Interface
        1. 6.14.2.1 SATA Interface Schematic
        2. 6.14.2.2 Compatible SATA Components and Modes
        3. 6.14.2.3 PCB Stackup Specifications
        4. 6.14.2.4 Routing Specifications
        5. 6.14.2.5 Coupling Capacitors
        6. 6.14.2.6 SATA Interface Clock Source requirements
      3. 6.14.3 SATA Unused Signal Configuration
    15. 6.15 Multichannel Audio Serial Port (McASP)
      1. 6.15.1 McASP Peripheral Registers Description(s)
      2. 6.15.2 McASP Electrical Data/Timing
        1. 6.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-54 Timing Requirements for McASP0 (1.3V, 1.2V, 1.1V)
          2. Table 6-55 Timing Requirements for McASP0 (1.0V)
          3. Table 6-56 Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)
          4. Table 6-57 Switching Characteristics for McASP0 (1.0V)
    16. 6.16 Multichannel Buffered Serial Port (McBSP)
      1. 6.16.1 McBSP Peripheral Register Description(s)
      2. 6.16.2 McBSP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Buffered Serial Port (McBSP) Timing
          1. Table 6-59 Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V] (see )
          2. Table 6-60 Timing Requirements for McBSP0 [1.0V] (see )
          3. Table 6-61 Switching Characteristics for McBSP0 [1.3V, 1.2V, 1.1V] (see )
          4. Table 6-62 Switching Characteristics for McBSP0 [1.0V] (see )
          5. Table 6-63 Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V] (see )
          6. Table 6-64 Timing Requirements for McBSP1 [1.0V] (see )
          7. Table 6-65 Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V] (see )
          8. Table 6-66 Switching Characteristics for McBSP1 [1.0V] (see )
          9. Table 6-67 Timing Requirements for McBSP0 FSR When GSYNC = 1 (see )
          10. Table 6-68 Timing Requirements for McBSP1 FSR When GSYNC = 1 (see )
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-70 General Timing Requirements for SPI0 Master Modes
          2. Table 6-71 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-78 General Timing Requirements for SPI1 Master Modes
          4. Table 6-79 General Timing Requirements for SPI1 Slave Modes
          5. Table 6-80 Additional SPI1 Master Timings, 4-Pin Enable Option
          6. Table 6-81 Additional SPI1 Master Timings, 4-Pin Chip Select Option
    18. 6.18 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.18.1 I2C Device-Specific Information
      2. 6.18.2 I2C Peripheral Registers Description(s)
      3. 6.18.3 I2C Electrical Data/Timing
        1. 6.18.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-87 Timing Requirements for I2C Input
          2. Table 6-88 Switching Characteristics for I2C
    19. 6.19 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.19.1 UART Peripheral Registers Description(s)
      2. 6.19.2 UART Electrical Data/Timing
        1. Table 6-90 Timing Requirements for UART Receive (see )
        2. Table 6-91 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    20. 6.20 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
      1. 6.20.1 USB0 [USB2.0] Electrical Data/Timing
        1. Table 6-93 Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see )
    21. 6.21 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]
      1. Table 6-95 Switching Characteristics Over Recommended Operating Conditions for USB1 [USB1.1]
    22. 6.22 Ethernet Media Access Controller (EMAC)
      1. 6.22.1 EMAC Peripheral Register Description(s)
        1. 6.22.1.1 EMAC Electrical Data/Timing
          1. Table 6-100 Timing Requirements for MII_RXCLK (see )
          2. Table 6-101 Timing Requirements for MII_TXCLK (see )
          3. Table 6-102 Timing Requirements for EMAC MII Receive 10/100 Mbit/s (see )
          4. Table 6-103 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s (see )
    23. 6.23 Management Data Input/Output (MDIO)
      1. 6.23.1 MDIO Register Description(s)
      2. 6.23.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-107 Timing Requirements for MDIO Input (see and )
        2. Table 6-108 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    24. 6.24 LCD Controller (LCDC)
      1. 6.24.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.24.2 LCD Raster Mode
        1. Table 6-112 Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode
    25. 6.25 Host-Port Interface (UHPI)
      1. 6.25.1 HPI Device-Specific Information
      2. 6.25.2 HPI Peripheral Register Description(s)
      3. 6.25.3 HPI Electrical Data/Timing
        1. Table 6-114 Timing Requirements for Host-Port Interface [1.2V, 1.1V]
        2. Table 6-115 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.3V, 1.2V, 1.1V]
        3. Table 6-116 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V]
    26. 6.26 Universal Parallel Port (uPP)
      1. 6.26.1 uPP Register Descriptions
        1. Table 6-117 Universal Parallel Port (uPP) Registers
      2. 6.26.2 uPP Electrical Data/Timing
        1. Table 6-118 Timing Requirements for uPP (see , , , )
        2. Table 6-119 Switching Characteristics Over Recommended Operating Conditions for uPP
    27. 6.27 Video Port Interface (VPIF)
      1. 6.27.1 VPIF Register Descriptions
        1. Table 6-120 Video Port Interface (VPIF) Registers
      2. 6.27.2 VPIF Electrical Data/Timing
        1. Table 6-121 Timing Requirements for VPIF VP_CLKINx Inputs (see )
        2. Table 6-122 Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs (see )
        3. Table 6-123 Switching Characteristics Over Recommended Operating Conditions for Video Data Shown With Respect to VP_CLKOUT2/3 (see )
    28. 6.28 Enhanced Capture (eCAP) Peripheral
      1. Table 6-125 Timing Requirements for Enhanced Capture (eCAP)
      2. Table 6-126 Switching Characteristics Over Recommended Operating Conditions for eCAP
    29. 6.29 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.29.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-128 Timing Requirements for eHRPWM
        2. Table 6-129 Switching Characteristics Over Recommended Operating Conditions for eHRPWM
      2. 6.29.2 Trip-Zone Input Timing
    30. 6.30 Timers
      1. 6.30.1 Timer Electrical Data/Timing
        1. Table 6-132 Timing Requirements for Timer Input (see )
        2. Table 6-133 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    31. 6.31 Real Time Clock (RTC)
      1. 6.31.1 Clock Source
      2. 6.31.2 Real-Time Clock Register Descriptions
    32. 6.32 General-Purpose Input/Output (GPIO)
      1. 6.32.1 GPIO Register Description(s)
      2. 6.32.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-136 Timing Requirements for GPIO Inputs (see )
        2. Table 6-137 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.32.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-138 Timing Requirements for External Interrupts (see )
    33. 6.33 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.33.1 PRUSS Register Descriptions
    34. 6.34 Emulation Logic
      1. 6.34.1 JTAG Port Description
      2. 6.34.2 Scan Chain Configuration Parameters
      3. 6.34.3 Initial Scan Chain Configuration
        1. 6.34.3.1 Adding TAPS to the Scan Chain
      4. 6.34.4 IEEE 1149.1 JTAG
        1. 6.34.4.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
        2. 6.34.4.2 JTAG Test-Port Electrical Data/Timing
          1. Table 6-150 Timing Requirements for JTAG Test Port (see )
          2. Table 6-151 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
      5. 6.34.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 社区资源
    5. 7.5 商标
    6. 7.6 静电放电警告
    7. 7.7 出口管制提示
    8. 7.8 术语表
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZCE Package
    2. 8.2 Thermal Data for ZWT Package
    3. 8.3 Packaging Information

Table 3-4 Top Level Memory Map

Start Address End Address Size ARM Mem Map DSP Mem Map EDMA Mem Map PRUSS Mem Map Master Peripheral Mem Map LCDC Mem Map
0x0000 0000 0x0000 0FFF 4K PRUSS Local Address Space
0x0000 1000 0x006F FFFF
0x0070 0000 0x007F FFFF 1024K DSP L2 ROM (1)
0x0080 0000 0x0083 FFFF 256K DSP L2 RAM
0x0084 0000 0x00DF FFFF
0x00E0 0000 0x00E0 7FFF 32K DSP L1P RAM
0x00E0 8000 0x00EF FFFF
0x00F0 0000 0x00F0 7FFF 32K DSP L1D RAM
0x00F0 8000 0x017F FFFF
0x0180 0000 0x0180 FFFF 64K DSP Interrupt Controller
0x0181 0000 0x0181 0FFF 4K DSP Powerdown Controller
0x0181 1000 0x0181 1FFF 4K DSP Security ID
0x0181 2000 0x0181 2FFF 4K DSP Revision ID
0x0181 3000 0x0181 FFFF 52K -
0x0182 0000 0x0182 FFFF 64K DSP EMC
0x0183 0000 0x0183 FFFF 64K DSP Internal Reserved
0x0184 0000 0x0184 FFFF 64K DSP Memory System
0x0185 0000 0x01BB FFFF
0x01BC 0000 0x01BC 0FFF 4K ARM ETB memory
0x01BC 1000 0x01BC 17FF 2K ARM ETB reg
0x01BC 1800 0x01BC 18FF 256 ARM Ice Crusher
0x01BC 1900 0x01BF FFFF
0x01C0 0000 0x01C0 7FFF 32K EDMA3 CC
0x01C0 8000 0x01C0 83FF 1K EDMA3 TC0
0x01C0 8400 0x01C0 87FF 1K EDMA3 TC1
0x01C0 8800 0x01C0 FFFF
0x01C1 0000 0x01C1 0FFF 4K PSC 0
0x01C1 1000 0x01C1 1FFF 4K PLL Controller 0
0x01C1 2000 0x01C1 3FFF
0x01C1 4000 0x01C1 4FFF 4K SYSCFG0
0x01C1 5000 0x01C1 FFFF
0x01C2 0000 0x01C2 0FFF 4K Timer0
0x01C2 1000 0x01C2 1FFF 4K Timer1
0x01C2 2000 0x01C2 2FFF 4K I2C 0
0x01C2 3000 0x01C2 3FFF 4K RTC
0x01C2 4000 0x01C3 FFFF
0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0
0x01C4 1000 0x01C4 1FFF 4K SPI 0
0x01C4 2000 0x01C4 2FFF 4K UART 0
0x01C4 3000 0x01CF FFFF
0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control
0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Ctrl
0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data
0x01D0 3000 0x01D0 BFFF
0x01D0 C000 0x01D0 CFFF 4K UART 1
0x01D0 D000 0x01D0 DFFF 4K UART 2
0x01D0 E000 0x01D0 FFFF
0x01D1 0000 0x01D1 07FF 2K McBSP0
0x01D1 0800 0x01D1 0FFF 2K McBSP0 FIFO Ctrl
0x01D1 1000 0x01D1 17FF 2K McBSP1
0x01D1 1800 0x01D1 1FFF 2K McBSP1 FIFO Ctrl
0x01D1 2000 0x01DF FFFF
0x01E0 0000 0x01E0 FFFF 64K USB0
0x01E1 0000 0x01E1 0FFF 4K UHPI
0x01E1 1000 0x01E1 2FFF
0x01E1 3000 0x01E1 3FFF 4K LCD Controller
0x01E1 4000 0x01E1 4FFF 4K Memory Protection Unit 1 (MPU 1)
0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 (MPU 2)
0x01E1 6000 0x01E1 6FFF 4K UPP
0x01E1 7000 0x01E1 7FFF 4K VPIF
0x01E1 8000 0x01E1 9FFF 8K SATA
0x01E1 A000 0x01E1 AFFF 4K PLL Controller 1
0x01E1 B000 0x01E1 BFFF 4K MMCSD1
0x01E1 C000 0x01E1 FFFF
0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM
0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers
0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers
0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port
0x01E2 5000 0x01E2 5FFF 4K USB1
0x01E2 6000 0x01E2 6FFF 4K GPIO
0x01E2 7000 0x01E2 7FFF 4K PSC 1
0x01E2 8000 0x01E2 8FFF 4K I2C 1
0x01E2 9000 0x01E2 BFFF
0x01E2 C000 0x01E2 CFFF 4K SYSCFG1
0x01E2 D000 0x01E2 FFFF
0x01E3 0000 0x01E3 7FFF 32K EDMA3 CC1
0x01E3 8000 0x01E3 83FF 1K EDMA3 TC2
0x01E3 8400 0x01EF FFFF
0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0
0x01F0 1000 0x01F0 1FFF 4K HRPWM 0
0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1
0x01F0 3000 0x01F0 3FFF 4K HRPWM 1
0x01F0 4000 0x01F0 5FFF
0x01F0 6000 0x01F0 6FFF 4K ECAP 0
0x01F0 7000 0x01F0 7FFF 4K ECAP 1
0x01F0 8000 0x01F0 8FFF 4K ECAP 2
0x01F0 9000 0x01F0 BFFF
0x01F0 C000 0x01F0 CFFF 4K Timer2
0x01F0 D000 0x01F0 DFFF 4K Timer3
0x01F0 E000 0x01F0 EFFF 4K SPI1
0x01F0 F000 0x01F0 FFFF
0x01F1 0000 0x01F1 0FFF 4K McBSP0 FIFO Data
0x01F1 1000 0x01F1 1FFF 4K McBSP1 FIFO Data
0x01F1 2000 0x116F FFFF
0x1170 0000 0x117F FFFF 1024K DSP L2 ROM(1)
0x1180 0000 0x1183 FFFF 256K DSP L2 RAM
0x1184 0000 0x11DF FFFF
0x11E0 0000 0x11E0 7FFF 32K DSP L1P RAM
0x11E0 8000 0x11EF FFFF
0x11F0 0000 0x11F0 7FFF 32K DSP L1D RAM
0x11F0 8000 0x3FFF FFFF
0x4000 0000 0x5FFF FFFF 512M EMIFA SDRAM data (CS0)
0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2)
0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3)
0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4)
0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5)
0x6800 0000 0x6800 7FFF 32K EMIFA Control Regs
0x6800 8000 0x7FFF FFFF
0x8000 0000 0x8001 FFFF 128K Shared RAM
0x8002 0000 0xAFFF FFFF
0xB000 0000 0xB000 7FFF 32K DDR2/mDDR Control Regs
0xB000 8000 0xBFFF FFFF
0xC000 0000 0xCFFF FFFF 256M DDR2/mDDR Data
0xD000 0000 0xFFFC FFFF
0xFFFD 0000 0xFFFD FFFF 64K ARM local ROM
0xFFFE 0000 0xFFFE DFFF
0xFFFE E000 0xFFFE FFFF 8K ARM Interrupt Controller
0xFFFF 0000 0xFFFF 1FFF 8K ARM local RAM ARM Local RAM (PRU0 only)
0xFFFF 2000 0xFFFF FFFF
(1) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code
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