ZHCSGV3G June   2009  – January 2017 TMS320C6748

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 DSP Memory Mapping
        1. 3.3.2.1 External Memories
        2. 3.3.2.2 DSP Internal Memories
        3. 3.3.2.3 C674x CPU
    4. 3.4 Memory Map Summary
      1. Table 3-4 C6748 Top Level Memory Map
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Pin Multiplexing Control
    7. 3.7 Terminal Functions
      1. 3.7.1  Device Reset, NMI and JTAG
      2. 3.7.2  High-Frequency Oscillator and PLL
      3. 3.7.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.7.4  DEEPSLEEP Power Control
      5. 3.7.5  External Memory Interface A (EMIFA)
      6. 3.7.6  DDR2/mDDR Controller
      7. 3.7.7  Serial Peripheral Interface Modules (SPI)
      8. 3.7.8  Programmable Real-Time Unit (PRU)
      9. 3.7.9  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      10. 3.7.10 Enhanced Pulse Width Modulators (eHRPWM)
      11. 3.7.11 Boot
      12. 3.7.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      13. 3.7.13 Inter-Integrated Circuit Modules(I2C0, I2C1)
      14. 3.7.14 Timers
      15. 3.7.15 Multichannel Audio Serial Ports (McASP)
      16. 3.7.16 Multichannel Buffered Serial Ports (McBSP)
      17. 3.7.17 Universal Serial Bus Modules (USB0, USB1)
      18. 3.7.18 Ethernet Media Access Controller (EMAC)
      19. 3.7.19 Multimedia Card/Secure Digital (MMC/SD)
      20. 3.7.20 Liquid Crystal Display Controller(LCD)
      21. 3.7.21 Serial ATA Controller (SATA)
      22. 3.7.22 Universal Host-Port Interface (UHPI)
      23. 3.7.23 Universal Parallel Port (uPP)
      24. 3.7.24 Video Port Interface (VPIF)
      25. 3.7.25 General Purpose Input Output
      26. 3.7.26 Reserved and No Connect
      27. 3.7.27 Supply and Ground
    8. 3.8 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 DSP Interrupts
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. 6.8.1.1 Power Domain States
        2. 6.8.1.2 Module States
    9. 6.9  Enhanced Direct Memory Access Controller (EDMA3)
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA3 Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface Register Descriptions
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-19 Timing Requirements for EMIFA SDRAM Interface
        2. Table 6-20 Switching Characteristics for EMIFA SDRAM Interface
        3. Table 6-21 Timing Requirements for EMIFA Asynchronous Memory Interface
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Memory Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1. 6.11.3.1  DDR2/mDDR Interface Schematic
        2. 6.11.3.2  Compatible JEDEC DDR2/mDDR Devices
        3. 6.11.3.3  PCB Stackup
        4. 6.11.3.4  Placement
        5. 6.11.3.5  DDR2/mDDR Keep Out Region
        6. 6.11.3.6  Bulk Bypass Capacitors
        7. 6.11.3.7  High-Speed Bypass Capacitors
        8. 6.11.3.8  Net Classes
        9. 6.11.3.9  DDR2/mDDR Signal Termination
        10. 6.11.3.10 VREF Routing
        11. 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
        12. 6.11.3.12 DDR2/mDDR Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
        1. Table 6-40 Timing Requirements for MMC/SD (see and )
        2. Table 6-41 Switching Characteristics for MMC/SD (see through )
    14. 6.14 Serial ATA Controller (SATA)
      1. 6.14.1 SATA Register Descriptions
      2. 6.14.2 1. SATA Interface
        1. 6.14.2.1 SATA Interface Schematic
        2. 6.14.2.2 Compatible SATA Components and Modes
        3. 6.14.2.3 PCB Stackup Specifications
        4. 6.14.2.4 Routing Specifications
        5. 6.14.2.5 Coupling Capacitors
        6. 6.14.2.6 SATA Interface Clock Source requirements
      3. 6.14.3 SATA Unused Signal Configuration
    15. 6.15 Multichannel Audio Serial Port (McASP)
      1. 6.15.1 McASP Peripheral Registers Description(s)
      2. 6.15.2 McASP Electrical Data/Timing
        1. 6.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-52 Timing Requirements for McASP0 (1.3V, 1.2V, 1.1V)
          2. Table 6-53 Timing Requirements for McASP0 (1.0V)
          3. Table 6-54 Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)
          4. Table 6-55 Switching Characteristics for McASP0 (1.0V)
    16. 6.16 Multichannel Buffered Serial Port (McBSP)
      1. 6.16.1 McBSP Peripheral Register Description(s)
      2. 6.16.2 McBSP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Buffered Serial Port (McBSP) Timing
          1. Table 6-57 Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V] (see )
          2. Table 6-58 Timing Requirements for McBSP0 [1.0V] (see )
          3. Table 6-59 Switching Characteristics for McBSP0 [1.3V, 1.2V, 1.1V] (see )
          4. Table 6-60 Switching Characteristics for McBSP0 [1.0V] (see )
          5. Table 6-61 Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V] (see )
          6. Table 6-62 Timing Requirements for McBSP1 [1.0V] (see )
          7. Table 6-63 Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V] (see )
          8. Table 6-64 Switching Characteristics for McBSP1 [1.0V] (see )
          9. Table 6-65 Timing Requirements for McBSP0 FSR When GSYNC = 1 (see )
          10. Table 6-66 Timing Requirements for McBSP1 FSR When GSYNC = 1 (see )
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-68 General Timing Requirements for SPI0 Master Modes
          2. Table 6-69 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-76 General Timing Requirements for SPI1 Master Modes
          4. Table 6-77 General Timing Requirements for SPI1 Slave Modes
          5. Table 6-78 Additional SPI1 Master Timings, 4-Pin Enable Option
          6. Table 6-79 Additional SPI1 Master Timings, 4-Pin Chip Select Option
    18. 6.18 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.18.1 I2C Device-Specific Information
      2. 6.18.2 I2C Peripheral Registers Description(s)
      3. 6.18.3 I2C Electrical Data/Timing
        1. 6.18.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-85 Timing Requirements for I2C Input
          2. Table 6-86 Switching Characteristics for I2C
    19. 6.19 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.19.1 UART Peripheral Registers Description(s)
      2. 6.19.2 UART Electrical Data/Timing
        1. Table 6-88 Timing Requirements for UART Receive (see )
        2. Table 6-89 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    20. 6.20 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
      1. 6.20.1 USB0 [USB2.0] Electrical Data/Timing
        1. Table 6-91 Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see )
    21. 6.21 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]
      1. Table 6-93 Switching Characteristics Over Recommended Operating Conditions for USB1 [USB1.1]
    22. 6.22 Ethernet Media Access Controller (EMAC)
      1. 6.22.1 EMAC Peripheral Register Description(s)
        1. 6.22.1.1 EMAC Electrical Data/Timing
          1. Table 6-98   Timing Requirements for MII_RXCLK (see )
          2. Table 6-99   Timing Requirements for MII_TXCLK (see )
          3. Table 6-100 Timing Requirements for EMAC MII Receive 10/100 Mbit/s (see )
          4. Table 6-101 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s (see )
    23. 6.23 Management Data Input/Output (MDIO)
      1. 6.23.1 MDIO Register Description(s)
      2. 6.23.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-105 Timing Requirements for MDIO Input (see and )
        2. Table 6-106 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    24. 6.24 LCD Controller (LCDC)
      1. 6.24.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.24.2 LCD Raster Mode
        1. Table 6-110 Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode
    25. 6.25 Host-Port Interface (UHPI)
      1. 6.25.1 HPI Device-Specific Information
      2. 6.25.2 HPI Peripheral Register Description(s)
      3. 6.25.3 HPI Electrical Data/Timing
        1. Table 6-112 Timing Requirements for Host-Port Interface [1.2V, 1.1V]
        2. Table 6-113 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.3V, 1.2V, 1.1V]
        3. Table 6-114 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V]
    26. 6.26 Universal Parallel Port (uPP)
      1. 6.26.1 uPP Register Descriptions
        1. Table 6-115 Universal Parallel Port (uPP) Registers
      2. 6.26.2 uPP Electrical Data/Timing
        1. Table 6-116 Timing Requirements for uPP (see , , , )
        2. Table 6-117 Switching Characteristics Over Recommended Operating Conditions for uPP
    27. 6.27 Video Port Interface (VPIF)
      1. 6.27.1 VPIF Register Descriptions
        1. Table 6-118 Video Port Interface (VPIF) Registers
      2. 6.27.2 VPIF Electrical Data/Timing
        1. Table 6-119 Timing Requirements for VPIF VP_CLKINx Inputs (see )
        2. Table 6-120 Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs (see )
        3. Table 6-121 Switching Characteristics Over Recommended Operating Conditions for Video Data Shown With Respect to VP_CLKOUT2/3 (see )
    28. 6.28 Enhanced Capture (eCAP) Peripheral
      1. Table 6-123 Timing Requirements for Enhanced Capture (eCAP)
      2. Table 6-124 Switching Characteristics Over Recommended Operating Conditions for eCAP
    29. 6.29 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.29.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-126 Timing Requirements for eHRPWM
        2. Table 6-127 Switching Characteristics Over Recommended Operating Conditions for eHRPWM
      2. 6.29.2 Trip-Zone Input Timing
    30. 6.30 Timers
      1. 6.30.1 Timer Electrical Data/Timing
        1. Table 6-130 Timing Requirements for Timer Input (see )
        2. Table 6-131 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    31. 6.31 Real Time Clock (RTC)
      1. 6.31.1 Clock Source
      2. 6.31.2 Real-Time Clock Register Descriptions
    32. 6.32 General-Purpose Input/Output (GPIO)
      1. 6.32.1 GPIO Register Description(s)
      2. 6.32.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-134 Timing Requirements for GPIO Inputs (see )
        2. Table 6-135 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.32.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-136 Timing Requirements for External Interrupts (see )
    33. 6.33 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.33.1 PRUSS Register Descriptions
    34. 6.34 Emulation Logic
      1. 6.34.1 JTAG Port Description
      2. 6.34.2 Scan Chain Configuration Parameters
      3. 6.34.3 Initial Scan Chain Configuration
      4. 6.34.4 IEEE 1149.1 JTAG
        1. 6.34.4.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
        2. 6.34.4.2 JTAG Test-Port Electrical Data/Timing
          1. Table 6-147 Timing Requirements for JTAG Test Port (see )
          2. Table 6-148 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
      5. 6.34.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 社区资源
    5. 7.5 商标
    6. 7.6 静电放电警告
    7. 7.7 出口管制提示
    8. 7.8 术语表
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZCE Package
    2. 8.2 Thermal Data for ZWT Package
    3. 8.3 Packaging Information

6.12 Memory Protection Units

The MPU performs memory protection checking. It receives requests from a bus master in the system and checks the address against the fixed and programmable regions to see if the access is allowed. If allowed, the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails the protection check) then the MPU does not pass the transfer to the output bus but rather services the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as well as generating an interrupt about the fault. The following features are supported by the MPU:

  • Provides memory protection for fixed and programmable address ranges.
  • Supports multiple programmable address region.
  • Supports secure and debug access privileges.
  • Supports read, write, and execute access privileges.
  • Supports privid(8) associations with ranges.
  • Generates an interrupt when there is a protection violation, and saves violating transfer parameters.
  • MMR access is also protected.

Table 6-37 MPU1 Configuration Registers

MPU1
BYTE ADDRESS		 ACRONYM REGISTER DESCRIPTION
0x01E1 4000 REVID Revision ID
0x01E1 4004 CONFIG Configuration
0x01E1 4010 IRAWSTAT Interrupt raw status/set
0x01E1 4014 IENSTAT Interrupt enable status/clear
0x01E1 4018 IENSET Interrupt enable
0x01E1 401C IENCLR Interrupt enable clear
0x01E1 4020 - 0x01E1 41FF - Reserved
0x01E1 4200 PROG1_MPSAR Programmable range 1, start address
0x01E1 4204 PROG1_MPEAR Programmable range 1, end address
0x01E1 4208 PROG1_MPPA Programmable range 1, memory page protection attributes
0x01E1 420C - 0x01E1 420F - Reserved
0x01E1 4210 PROG2_MPSAR Programmable range 2, start address
0x01E1 4214 PROG2_MPEAR Programmable range 2, end address
0x01E1 4218 PROG2_MPPA Programmable range 2, memory page protection attributes
0x01E1 421C - 0x01E1 421F - Reserved
0x01E1 4220 PROG3_MPSAR Programmable range 3, start address
0x01E1 4224 PROG3_MPEAR Programmable range 3, end address
0x01E1 4228 PROG3_MPPA Programmable range 3, memory page protection attributes
0x01E1 422C - 0x01E1 422F - Reserved
0x01E1 4230 PROG4_MPSAR Programmable range 4, start address
0x01E1 4234 PROG4_MPEAR Programmable range 4, end address
0x01E1 4238 PROG4_MPPA Programmable range 4, memory page protection attributes
0x01E1 423C - 0x01E1 423F - Reserved
0x01E1 4240 PROG5_MPSAR Programmable range 5, start address
0x01E1 4244 PROG5_MPEAR Programmable range 5, end address
0x01E1 4248 PROG5_MPPA Programmable range 5, memory page protection attributes
0x01E1 424C - 0x01E1 424F - Reserved
0x01E1 4250 PROG6_MPSAR Programmable range 6, start address
0x01E1 4254 PROG6_MPEAR Programmable range 6, end address
0x01E1 4258 PROG6_MPPA Programmable range 6, memory page protection attributes
0x01E1 425C - 0x01E1 42FF - Reserved
0x01E1 4300 FLTADDRR Fault address
0x01E1 4304 FLTSTAT Fault status
0x01E1 4308 FLTCLR Fault clear
0x01E1 430C - 0x01E1 4FFF - Reserved

Table 6-38 MPU2 Configuration Registers

MPU2
BYTE ADDRESS		 ACRONYM REGISTER DESCRIPTION
0x01E1 5000 REVID Revision ID
0x01E1 5004 CONFIG Configuration
0x01E1 5010 IRAWSTAT Interrupt raw status/set
0x01E1 5014 IENSTAT Interrupt enable status/clear
0x01E1 5018 IENSET Interrupt enable
0x01E1 501C IENCLR Interrupt enable clear
0x01E1 5020 - 0x01E1 51FF - Reserved
0x01E1 5200 PROG1_MPSAR Programmable range 1, start address
0x01E1 5204 PROG1_MPEAR Programmable range 1, end address
0x01E1 5208 PROG1_MPPA Programmable range 1, memory page protection attributes
0x01E1 520C - 0x01E1 520F - Reserved
0x01E1 5210 PROG2_MPSAR Programmable range 2, start address
0x01E1 5214 PROG2_MPEAR Programmable range 2, end address
0x01E1 5218 PROG2_MPPA Programmable range 2, memory page protection attributes
0x01E1 521C - 0x01E1 521F - Reserved
0x01E1 5220 PROG3_MPSAR Programmable range 3, start address
0x01E1 5224 PROG3_MPEAR Programmable range 3, end address
0x01E1 5228 PROG3_MPPA Programmable range 3, memory page protection attributes
0x01E1 522C - 0x01E1 522F - Reserved
0x01E1 5230 PROG4_MPSAR Programmable range 4, start address
0x01E1 5234 PROG4_MPEAR Programmable range 4, end address
0x01E1 5238 PROG4_MPPA Programmable range 4, memory page protection attributes
0x01E1 523C - 0x01E1 523F - Reserved
0x01E1 5240 PROG5_MPSAR Programmable range 5, start address
0x01E1 5244 PROG5_MPEAR Programmable range 5, end address
0x01E1 5248 PROG5_MPPA Programmable range 5, memory page protection attributes
0x01E1 524C - 0x01E1 524F - Reserved
0x01E1 5250 PROG6_MPSAR Programmable range 6, start address
0x01E1 5254 PROG6_MPEAR Programmable range 6, end address
0x01E1 5258 PROG6_MPPA Programmable range 6, memory page protection attributes
0x01E1 525C - 0x01E1 525F - Reserved
0x01E1 5260 PROG7_MPSAR Programmable range 7, start address
0x01E1 5264 PROG7_MPEAR Programmable range 7, end address
0x01E1 5268 PROG7_MPPA Programmable range 7, memory page protection attributes
0x01E1 526C - 0x01E1 526F - Reserved
0x01E1 5270 PROG8_MPSAR Programmable range 8, start address
0x01E1 5274 PROG8_MPEAR Programmable range 8, end address
0x01E1 5278 PROG8_MPPA Programmable range 8, memory page protection attributes
0x01E1 527C - 0x01E1 527F - Reserved
0x01E1 5280 PROG9_MPSAR Programmable range 9, start address
0x01E1 5284 PROG9_MPEAR Programmable range 9, end address
0x01E1 5288 PROG9_MPPA Programmable range 9, memory page protection attributes
0x01E1 528C - 0x01E1 528F - Reserved
0x01E1 5290 PROG10_MPSAR Programmable range 10, start address
0x01E1 5294 PROG10_MPEAR Programmable range 10, end address
0x01E1 5298 PROG10_MPPA Programmable range 10, memory page protection attributes
0x01E1 529C - 0x01E1 529F - Reserved
0x01E1 52A0 PROG11_MPSAR Programmable range 11, start address
0x01E1 52A4 PROG11_MPEAR Programmable range 11, end address
0x01E1 52A8 PROG11_MPPA Programmable range 11, memory page protection attributes
0x01E1 52AC - 0x01E1 52AF - Reserved
0x01E1 52B0 PROG12_MPSAR Programmable range 12, start address
0x01E1 52B4 PROG12_MPEAR Programmable range 12, end address
0x01E1 52B8 PROG12_MPPA Programmable range 12, memory page protection attributes
0x01E1 52BC - 0x01E1 52FF - Reserved
0x01E1 5300 FLTADDRR Fault address
0x01E1 5304 FLTSTAT Fault status
0x01E1 5308 FLTCLR Fault clear
0x01E1 530C - 0x01E1 5FFF - Reserved
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