米6体育平台手机版

ZHCSGV3G June 2009 – January 2017 TMS320C6748

PRODUCTION DATA.

Table 6-79 Additional⁽⁷⁾ SPI1 Master Timings, 4-Pin Chip Select Option⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
19	t_{d(SCS_SPC)M}	Delay from SPI1_SCS active to first SPI1_CLK⁽³⁾⁽⁴⁾	Polarity = 0, Phase = 0, to SPI1_CLK rising	2P-1		2P-5		2P-6		ns
			Polarity = 0, Phase = 1, to SPI1_CLK rising	0.5M+2P-1		0.5M+2P-5		0.5M+2P-6
			Polarity = 1, Phase = 0, to SPI1_CLK falling	2P-1		2P-5		2P-6
			Polarity = 1, Phase = 1, to SPI1_CLK falling	0.5M+2P-1		0.5M+2P-5		0.5M+2P-6
20	t_{d(SPC_SCS)M}	Delay from final SPI1_CLK edge to master deasserting SPI1_SCS⁽⁵⁾⁽⁶⁾	Polarity = 0, Phase = 0, from SPI1_CLK falling	0.5M+P-1		0.5M+P-5		0.5M+P-6		ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling	P-1		P-5		P-6
			Polarity = 1, Phase = 0, from SPI1_CLK rising	0.5M+P-1		0.5M+P-5		0.5M+P-6
			Polarity = 1, Phase = 1, from SPI1_CLK rising	P-1		P-5		P-6

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(3) In the case where the master SPI is ready with new data before SPI1_SCS assertion.

(4) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.

(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

(7) These parameters are in addition to the general timings for SPI master modes (Table 6-76).

Table 6-80 Additional⁽¹⁰⁾ SPI1 Master Timings, 5-Pin Option⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
18	t_{d(SPC_ENA)M}	Max delay for slave to deassert SPI1_ENA after final SPI1_CLK edge to ensure master does not begin the next transfer.⁽³⁾	Polarity = 0, Phase = 0, from SPI1_CLK falling		0.5M+P+5		0.5M+P+5		0.5M+P+6	ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling		P+5		P+5		P+6
			Polarity = 1, Phase = 0, from SPI1_CLK rising		0.5M+P+5		0.5M+P+5		0.5M+P+6
			Polarity = 1, Phase = 1, from SPI1_CLK rising		P+5		P+5		P+6
20	t_{d(SPC_SCS)M}	Delay from final SPI1_CLK edge to master deasserting SPI1_SCS⁽⁴⁾⁽⁵⁾	Polarity = 0, Phase = 0, from SPI1_CLK falling	0.5M+P-1		0.5M+P-5		0.5M+P-6		ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling	P-1		P-5		P-6
			Polarity = 1, Phase = 0, from SPI1_CLK rising	0.5M+P-1		0.5M+P-5		0.5M+P-6
			Polarity = 1, Phase = 1, from SPI1_CLK rising	P-1		P-5		P-6
21	t_{d(SCSL_ENAL)M}	Max delay for slave SPI to drive SPI1_ENA valid after master asserts SPI1_SCS to delay the master from beginning the next transfer,		C2TDELAY+P		C2TDELAY+P		C2TDELAY+P		ns
22	t_{d(SCS_SPC)M}	Delay from SPI1_SCS active to first SPI1_CLK⁽⁶⁾⁽⁷⁾⁽⁸⁾	Polarity = 0, Phase = 0, to SPI1_CLK rising	2P-1		2P-5		2P-6		ns
			Polarity = 0, Phase = 1, to SPI1_CLK rising	0.5M+2P-1		0.5M+2P-5		0.5M+2P-6
			Polarity = 1, Phase = 0, to SPI1_CLK falling	2P-1		2P-5		2P-6
			Polarity = 1, Phase = 1, to SPI1_CLK falling	0.5M+2P-1		0.5M+2P-5		0.5M+2P-6
23	t_{d(ENA_SPC)M}	Delay from assertion of SPI1_ENA low to first SPI1_CLK edge.⁽⁹⁾	Polarity = 0, Phase = 0, to SPI1_CLK rising		3P+5		3P+5		3P+6	ns
			Polarity = 0, Phase = 1, to SPI1_CLK rising	0.5M+3P+5		0.5M+3P+5		0.5M+3P+6
			Polarity = 1, Phase = 0, to SPI1_CLK falling		3P+5		3P+5		3P+6
			Polarity = 1, Phase = 1, to SPI1_CLK falling	0.5M+3P+5		0.5M+3P+5		0.5M+3P+6

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(3) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.

(4) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.

(5) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

(6) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.

(7) In the case where the master SPI is ready with new data before SPI1_SCS assertion.

(8) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(9) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.

(10) These parameters are in addition to the general timings for SPI master modes (Table 6-77).

Table 6-81 Additional⁽³⁾ SPI1 Slave Timings, 4-Pin Enable Option⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
24	t_{d(SPC_ENAH)S}	Delay from final SPI1_CLK edge to slave deasserting SPI1_ENA.	Polarity = 0, Phase = 0, from SPI1_CLK falling	1.5P-3	2.5P+15	1.5P-10	2.5P+17	1.5P-12	2.5P+19	ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling	–0.5M+1.5P-3	–0.5M+2.5P+15	–0.5M+1.5P-10	–0.5M+2.5P+17	–0.5M+1.5P-12	–0.5M+2.5P+19
			Polarity = 1, Phase = 0, from SPI1_CLK rising	1.5P-3	2.5P+15	1.5P-10	2.5P+17	1.5P-12	2.5P+19
			Polarity = 1, Phase = 1, from SPI1_CLK rising	–0.5M+1.5P-3	–0.5M+2.5P+15	–0.5M+1.5P-10	–0.5M+2.5P+17	–0.5M+1.5P-12	–0.5M+2.5P+19

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(3) These parameters are in addition to the general timings for SPI slave modes (Table 6-77).

Table 6-82 Additional⁽³⁾ SPI1 Slave Timings, 4-Pin Chip Select Option⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
25	t_{d(SCSL_SPC)S}	Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave.		P+1.5		P+1.5		P+1.5		ns
26	t_{d(SPC_SCSH)S}	Required delay from final SPI1_CLK edge before SPI1_SCS is deasserted.	Polarity = 0, Phase = 0, from SPI1_CLK falling	0.5M+P+4		0.5M+P+5		0.5M+P+6		ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling	P+4		P+5		P+6
			Polarity = 1, Phase = 0, from SPI1_CLK rising	0.5M+P+4		0.5M+P+5		0.5M+P+6
			Polarity = 1, Phase = 1, from SPI1_CLK rising	P+4		P+5		P+6
27	t_{ena(SCSL_SOMI)S}	Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid			P+15		P+17		P+19	ns
28	t_{dis(SCSH_SOMI)S}	Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI			P+15		P+17		P+19	ns

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(3) These parameters are in addition to the general timings for SPI slave modes (Table 6-77).

Table 6-83 Additional⁽⁴⁾ SPI1 Slave Timings, 5-Pin Option⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
25	t_{d(SCSL_SPC)S}	Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave.		P+1.5		P+1.5		P+1.5		ns
26	t_{d(SPC_SCSH)S}	Required delay from final SPI1_CLK edge before SPI1_SCS is deasserted.	Polarity = 0, Phase = 0, from SPI1_CLK falling	0.5M+P+4		0.5M+P+5		0.5M+P+6		ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling	P+4		P+5		P+6
			Polarity = 1, Phase = 0, from SPI1_CLK rising	0.5M+P+4		0.5M+P+5		0.5M+P+6
			Polarity = 1, Phase = 1, from SPI1_CLK rising	P+4		P+5		P+6
27	t_{ena(SCSL_SOMI)S}	Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid			P+15		P+17		P+19	ns
28	t_{dis(SCSH_SOMI)S}	Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI			P+15		P+17		P+19	ns
29	t_{ena(SCSL_ENA)S}	Delay from master deasserting SPI1_SCS to slave driving SPI1_ENA valid			15		17		19	ns
30	t_{dis(SPC_ENA)S}	Delay from final clock receive edge on SPI1_CLK to slave 3-stating or driving high SPI1_ENA.⁽³⁾	Polarity = 0, Phase = 0, from SPI1_CLK falling		2.5P+15		2.5P+17		2.5P+19	ns
			Polarity = 0, Phase = 1, from SPI1_CLK rising		2.5P+15		2.5P+17		2.5P+19
			Polarity = 1, Phase = 0, from SPI1_CLK rising		2.5P+15		2.5P+17		2.5P+19
			Polarity = 1, Phase = 1, from SPI1_CLK falling		2.5P+15		2.5P+17		2.5P+19

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(3) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.

(4) These parameters are in addition to the general timings for SPI slave modes (Table 6-77).

Figure 6-38 SPI Timings—Master Mode

Figure 6-39 SPI Timings—Slave Mode

Figure 6-40 SPI Timings—Master Mode (4-Pin and 5-Pin)

Figure 6-41 SPI Timings—Slave Mode (4-Pin and 5-Pin)

Table 6-79 Additional(7) SPI1 Master Timings, 4-Pin Chip Select Option(1)(2)

Table 6-80 Additional(10) SPI1 Master Timings, 5-Pin Option(1)(2)

Table 6-81 Additional(3) SPI1 Slave Timings, 4-Pin Enable Option(1)(2)

Table 6-82 Additional(3) SPI1 Slave Timings, 4-Pin Chip Select Option(1)(2)

Table 6-83 Additional(4) SPI1 Slave Timings, 5-Pin Option(1)(2)

Table 6-79 Additional⁽⁷⁾ SPI1 Master Timings, 4-Pin Chip Select Option⁽¹⁾⁽²⁾

Table 6-80 Additional⁽¹⁰⁾ SPI1 Master Timings, 5-Pin Option⁽¹⁾⁽²⁾

Table 6-81 Additional⁽³⁾ SPI1 Slave Timings, 4-Pin Enable Option⁽¹⁾⁽²⁾

Table 6-82 Additional⁽³⁾ SPI1 Slave Timings, 4-Pin Chip Select Option⁽¹⁾⁽²⁾

Table 6-83 Additional⁽⁴⁾ SPI1 Slave Timings, 5-Pin Option⁽¹⁾⁽²⁾