6.6.1 PLL Device-Specific Information

The device DSP generates the high-frequency internal clocks it requires through an on-chip PLL.

The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-8.

Figure 6-8 PLL External Filtering Components

The external filtering components shown above provide noise immunity for the PLLs. PLL0_VDDA and PLL1_VDDA should not be connected together to provide noise immunity between the two PLLs. Likewise, PLL0_VSSA and PLL1_VSSA should not be connected together.

The input to the PLL is either from the on-chip oscillator or from an external clock on the OSCIN pin. PLL0 outputs seven clocks that have programmable divider options. PLL1 outputs three clocks that have programmable divider options. Figure 6-9 illustrates the high-level view of the PLL Topology.

The PLLs are disabled by default after a device reset. They must be configured by software according to the allowable operating conditions listed in Table 6-4 before enabling the device to run from the PLL by setting PLLEN = 1.

Figure 6-9 PLL Topology

Table 6-4 Allowed PLL Operating Conditions (PLL0 and PLL1)

NO.	PARAMETER	Default Value	MIN	MAX	UNIT
1	PLLRST: Assertion time during initialization	N/A	1000	N/A	ns
2	Lock time: The time that the application has to wait for the PLL to acquire lock before setting PLLEN, after changing PREDIV, PLLM, or OSCIN	N/A	N/A	(1)	OSCIN cycles
3	PREDIV: Pre-divider value	/1	/1	/32	-
4	PLLREF: PLL input frequency		12	30 (if internal oscillator is used) 50 (if external clock is used)	MHz
5	PLLM: PLL multiplier values	x20	x4	x32
6	PLLOUT: PLL output frequency	N/A	300	600	MHz
7	POSTDIV: Post-divider value	/1	/1	/32	-

(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 300 and 600 MHz, but the frequency going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given voltage operating point.