ZHCSGV7F July   2017  – January 2024 CDCI6214

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  EEPROM Characteristics
    6. 6.6  Reference Input, Single-Ended and Differential Mode Characteristics (REFP, REFN, FB_P, FB_N)
    7. 6.7  Reference Input, Crystal Mode Characteristics (XIN, XOUT)
    8. 6.8  General-Purpose Input and Output Characteristics (GPIO[4:1], SYNC/RESETN)
    9. 6.9  Triple Level Input Characteristics (EEPROMSEL, REFSEL)
    10. 6.10 Reference Mux Characteristics
    11. 6.11 Phase-Locked Loop Characteristics
    12. 6.12 Closed-Loop Output Jitter Characteristics
    13. 6.13 Output Mux Characteristics
    14. 6.14 LVCMOS Output Characteristics
    15. 6.15 HCSL Output Characteristics
    16. 6.16 LVDS DC-Coupled Output Characteristics
    17. 6.17 Programmable Differential AC-Coupled Output Characteristics
    18. 6.18 Output Skew and Delay Characteristics
    19. 6.19 Output Synchronization Characteristics
    20. 6.20 Timing Characteristics
    21. 6.21 I2C-Compatible Serial Interface Characteristics (SDA/GPIO2, SCL/GPIO3)
    22. 6.22 Timing Requirements, I2C-Compatible Serial Interface (SDA/GPIO2, SCL/GPIO3)
    23. 6.23 Power Supply Characteristics
    24. 6.24 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Parameters
      1. 7.1.1 Reference Inputs
      2. 7.1.2 Outputs
      3. 7.1.3 Serial Interface
      4. 7.1.4 Power Supply
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference Block
        1. 8.3.1.1 Input Stages
          1. 8.3.1.1.1 Crystal Oscillator
          2. 8.3.1.1.2 LVCMOS
          3. 8.3.1.1.3 Differential AC-Coupled
        2. 8.3.1.2 Reference Mux
        3. 8.3.1.3 Reference Divider
          1. 8.3.1.3.1 Doubler
        4. 8.3.1.4 Bypass-Mux
        5. 8.3.1.5 Zero Delay, Internal and External Path
      2. 8.3.2 Phase-Locked Loop
      3. 8.3.3 Clock Distribution
        1. 8.3.3.1 Output Channel
        2. 8.3.3.2 Divider Glitch-Less Update
      4. 8.3.4 Control Pins
        1. 8.3.4.1 Global and Individual Output Enable: OE and OE_Y[4:1]
      5. 8.3.5 Operation Modes
      6. 8.3.6 Divider Synchronization - SYNC
      7. 8.3.7 EEPROM - Cyclic Redundancy Check
      8. 8.3.8 Power Supplies
        1. 8.3.8.1 Power Management
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Mode
      2. 8.4.2 Serial Interface Mode
        1. 8.4.2.1 Fall-Back Mode
    5. 8.5 Programming
      1. 8.5.1 Recommended Programming Procedure
      2. 8.5.2 EEPROM Access
      3. 8.5.3 Device Defaults
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Setup
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Power-Up Sequence
      2. 9.5.2 De-Coupling
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Examples
  11. 10Register Maps
    1. 10.1 CDCI6214 Registers
    2. 10.2 EEPROM Map
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Device Nomenclature
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

10.2 EEPROM Map

The EEPROM is split into a common base page which holds common settings. Then there are two pages for customized settings. Page 0 is selected using EEPROMSEL = Low. Page 1 is selected using EEPROMSEL = High.

The CRC value is stored at the end of page 1 in word 0x3F.

Table 10-59 EEPROM, Base
WORD NO.SECTION1514131211109876543210
0hBasecp_dly[0]cal_muteshift_left[1]shift_left[0]gpio3_gf_engpio2_gf_enacal_enpdn_pll_vcobuf2pdn_pll_vcopdn_pll_vcobufpdn_pll_cppdn_pll_lockdetpdn_pll_pfdpdn_pll_psfbregcommit_pageresetn_soft
1hBaseac_cmp_dly[0]pll_lock_dly[4]pll_lock_dly[3]pll_lock_dly[2]pll_lock_dly[1]pll_lock_dly[0]ac_init_dly[5]ac_init_dly[4]ac_init_dly[3]ac_init_dly[2]ac_init_dly[1]ac_init_dly[0]cp_dly[4]cp_dly[3]cp_dly[2]cp_dly[1]
2hBase000000err_cnt[2]err_cnt[1]err_cnt[0]fc_setl_dly[1]fc_setl_dly[0]ac_cmp_dly[5]ac_cmp_dly[4]ac_cmp_dly[3]ac_cmp_dly[2]ac_cmp_dly[1]
3hBasepll_pfd_dly_ctrl[1]pll_pfd_dly_ctrl[0]pll_lockdet_window[2]pll_lockdet_window[1]pll_lockdet_window[0]pll_lockdet_wait[1]pll_lockdet_wait[0]000000000
4hBase0001010000000000
5hBasechx_diffbuf_ibias_trim[1]chx_diffbuf_ibias_trim[0]chx_lvcmos_drvchx_en_cmosslow000100000100
6hBase0000110000chx_lvds_cmtrim_inc[1]chx_lvds_cmtrim_inc[0]chx_lvds_cmtrim_dec[1]chx_lvds_cmtrim_dec[0]chx_diffbuf_ibias_trim[3]chx_diffbuf_ibias_trim[2]
7hBase0101000000000000
8hBase0000100001100001
9hBase1000010000100001
AhBase0000000000000110
BhBase0000000000000000
Table 10-60 EEPROM, Page 0
WORD NO.SECTION1514131211109876543210
ChPage 0gpio4_input_sel[3]gpio4_input_sel[2]gpio4_input_sel[1]gpio4_input_sel[0]gpio1_input_sel[3]gpio1_input_sel[2]gpio1_input_sel[1]gpio1_input_sel[0]i2c_a0gpio0_input_selgpio4_dir_selgpio1_dir_selgpio0_dir_selzdm_clockselzdm_modemode
DhPage 0gpio4_output_sel[3]gpio4_output_sel[2]gpio4_output_sel[1]gpio4_output_sel[0]gpio1_output_sel[3]gpio1_output_sel[2]gpio1_output_sel[1]gpio1_output_sel[0]011010ref_mux_srcref_mux
EhPage 01pdn_ch41pdn_ch31pdn_ch21pdn_ch110rsrvd_1[1]rsrvd_1[0]gpio0_output_sel[3]gpio0_output_sel[2]gpio0_output_sel[1]gpio0_output_sel[0]
FhPage 0ip_xo_cload[2]ip_xo_cload[1]ip_xo_cload[0]00ip_xo_gm[3]ip_xo_gm[2]ip_xo_gm[1]ip_xo_gm[0]xin_inbuf_ctrl[1]xin_inbuf_ctrl[0]zdm_autobypass_calbypass_configpdn_pll_psbpdn_pll_psa
10hPage 0ip_byp_en_ch3ip_byp_en_ch2ip_byp_en_ch1ip_byp_en_y0ip_byp_muxip_rdiv[7]ip_rdiv[6]ip_rdiv[5]ip_rdiv[4]ip_rdiv[3]ip_rdiv[2]ip_rdiv[1]ip_rdiv[0]ref_inbuf_ctrlip_xo_cload[4]ip_xo_cload[3]
11hPage 0pll_ndiv[13]pll_ndiv[12]pll_ndiv[11]pll_ndiv[10]pll_ndiv[9]pll_ndiv[8]pll_ndiv[7]pll_ndiv[6]pll_ndiv[5]pll_ndiv[4]pll_ndiv[3]pll_ndiv[2]pll_ndiv[1]pll_ndiv[0]0ip_byp_en_ch4
12hPage 0pll_cp_up[3]pll_cp_up[2]pll_cp_up[1]pll_cp_up[0]pll_cp_dn[5]pll_cp_dn[4]pll_cp_dn[3]pll_cp_dn[2]pll_cp_dn[1]pll_cp_dn[0]pll_psb[1]pll_psb[0]pll_psa[1]pll_psa[0]pll_psfb[1]pll_psfb[0]
13hPage 0pll_lf_zcap[4]pll_lf_zcap[3]pll_lf_zcap[2]pll_lf_zcap[1]pll_lf_zcap[0]pll_lf_res[3]pll_lf_res[2]pll_lf_res[1]pll_lf_res[0]pll_lf_pcap[4]pll_lf_pcap[3]pll_lf_pcap[2]pll_lf_pcap[1]pll_lf_pcap[0]pll_cp_up[5]pll_cp_up[4]
14hPage 01000000000000000
15hPage 0ch1_iod_div[6]ch1_iod_div[5]ch1_iod_div[4]ch1_iod_div[3]ch1_iod_div[2]ch1_iod_div[1]ch1_iod_div[0]000000000
16hPage 000ch1_outbuf_ctrl[2]ch1_outbuf_ctrl[1]ch1_outbuf_ctrl[0]ch1_mux[1]ch1_mux[0]ch1_iod_mux[1]ch1_iod_mux[0]ch1_iod_div[13]ch1_iod_div[12]ch1_iod_div[11]ch1_iod_div[10]ch1_iod_div[9]ch1_iod_div[8]ch1_iod_div[7]
17hPage 00010100ch1_glitchless_ench1_sync_delay[4]ch1_sync_delay[3]ch1_sync_delay[2]ch1_sync_delay[1]ch1_sync_delay[0]ch1_sync_ench1_mute_selch1_mute
18hPage 000000000000000ch1_1p8vdet0
19hPage 0ch2_iod_div[4]ch2_iod_div[3]ch2_iod_div[2]ch2_iod_div[1]ch2_iod_div[0]00000000010
1AhPage 0ch2_outbuf_ctrl[2]ch2_outbuf_ctrl[1]ch2_outbuf_ctrl[0]ch2_mux[1]ch2_mux[0]ch2_iod_mux[1]ch2_iod_mux[0]ch2_iod_div[13]ch2_iod_div[12]ch2_iod_div[11]ch2_iod_div[10]ch2_iod_div[9]ch2_iod_div[8]ch2_iod_div[7]ch2_iod_div[6]ch2_iod_div[5]
1BhPage 010100ch2_glitchless_ench2_sync_delay[4]ch2_sync_delay[3]ch2_sync_delay[2]ch2_sync_delay[1]ch2_sync_delay[0]ch2_sync_ench2_mute_selch2_mutech2_cmos_pol[1]ch2_cmos_pol[0]
1ChPage 0000000000000ch2_1p8vdet000
1DhPage 0ch3_iod_div[2]ch3_iod_div[1]ch3_iod_div[0]0000000001000
1EhPage 0ch3_outbuf_ctrl[0]ch3_mux[1]ch3_mux[0]ch3_iod_mux[1]ch3_iod_mux[0]ch3_iod_div[13]ch3_iod_div[12]ch3_iod_div[11]ch3_iod_div[10]ch3_iod_div[9]ch3_iod_div[8]ch3_iod_div[7]ch3_iod_div[6]ch3_iod_div[5]ch3_iod_div[4]ch3_iod_div[3]
1FhPage 0000ch3_glitchless_ench3_sync_delay[4]ch3_sync_delay[3]ch3_sync_delay[2]ch3_sync_delay[1]ch3_sync_delay[0]ch3_sync_ench3_mute_selch3_mutech3_cmos_pol[1]ch3_cmos_pol[0]ch3_outbuf_ctrl[2]ch3_outbuf_ctrl[1]
20hPage 00000000000ch3_1p8vdet10010
21hPage 0ch4_iod_div[0]000000000100000
22hPage 0ch4_mux[0]ch4_iod_mux[1]ch4_iod_mux[0]ch4_iod_div[13]ch4_iod_div[12]ch4_iod_div[11]ch4_iod_div[10]ch4_iod_div[9]ch4_iod_div[8]ch4_iod_div[7]ch4_iod_div[6]ch4_iod_div[5]ch4_iod_div[4]ch4_iod_div[3]ch4_iod_div[2]ch4_iod_div[1]
23hPage 00ch4_glitchless_ench4_sync_delay[4]ch4_sync_delay[3]ch4_sync_delay[2]ch4_sync_delay[1]ch4_sync_delay[0]ch4_sync_ench4_mute_selch4_mute00ch4_outbuf_ctrl[2]ch4_outbuf_ctrl[1]ch4_outbuf_ctrl[0]ch4_mux[1]
24hPage 00011pll_en_cpch0_lvcmos_drv[1]ch0_lvcmos_drv[0]1ch4_1p8vdet1001010
25hPage 00000000000000000
Table 10-61 EEPROM, Page 1
WORD NO.SECTION1514131211109876543210
26hPage 1gpio4_input_sel[3]gpio4_input_sel[2]gpio4_input_sel[1]gpio4_input_sel[0]gpio1_input_sel[3]gpio1_input_sel[2]gpio1_input_sel[1]gpio1_input_sel[0]i2c_a0gpio0_input_selgpio4_dir_selgpio1_dir_selgpio0_dir_selzdm_clockselzdm_modemode
27hPage 1gpio4_output_sel[3]gpio4_output_sel[2]gpio4_output_sel[1]gpio4_output_sel[0]gpio1_output_sel[3]gpio1_output_sel[2]gpio1_output_sel[1]gpio1_output_sel[0]011010ref_mux_srcref_mux
28hPage 11pdn_ch41pdn_ch31pdn_ch21pdn_ch110rsrvd_1[1]rsrvd_1[0]gpio0_output_sel[3]gpio0_output_sel[2]gpio0_output_sel[1]gpio0_output_sel[0]
29hPage 1ip_xo_cload[2]ip_xo_cload[1]ip_xo_cload[0]00ip_xo_gm[3]ip_xo_gm[2]ip_xo_gm[1]ip_xo_gm[0]xin_inbuf_ctrl[1]xin_inbuf_ctrl[0]zdm_autobypass_calbypass_configpdn_pll_psbpdn_pll_psa
2AhPage 1ip_byp_en_ch3ip_byp_en_ch2ip_byp_en_ch1ip_byp_en_y0ip_byp_muxip_rdiv[7]ip_rdiv[6]ip_rdiv[5]ip_rdiv[4]ip_rdiv[3]ip_rdiv[2]ip_rdiv[1]ip_rdiv[0]ref_inbuf_ctrlip_xo_cload[4]ip_xo_cload[3]
2BhPage 1pll_ndiv[13]pll_ndiv[12]pll_ndiv[11]pll_ndiv[10]pll_ndiv[9]pll_ndiv[8]pll_ndiv[7]pll_ndiv[6]pll_ndiv[5]pll_ndiv[4]pll_ndiv[3]pll_ndiv[2]pll_ndiv[1]pll_ndiv[0]0ip_byp_en_ch4
2ChPage 1pll_cp_up[3]pll_cp_up[2]pll_cp_up[1]pll_cp_up[0]pll_cp_dn[5]pll_cp_dn[4]pll_cp_dn[3]pll_cp_dn[2]pll_cp_dn[1]pll_cp_dn[0]pll_psb[1]pll_psb[0]pll_psa[1]pll_psa[0]pll_psfb[1]pll_psfb[0]
2DhPage 1pll_lf_zcap[4]pll_lf_zcap[3]pll_lf_zcap[2]pll_lf_zcap[1]pll_lf_zcap[0]pll_lf_res[3]pll_lf_res[2]pll_lf_res[1]pll_lf_res[0]pll_lf_pcap[4]pll_lf_pcap[3]pll_lf_pcap[2]pll_lf_pcap[1]pll_lf_pcap[0]pll_cp_up[5]pll_cp_up[4]
2EhPage 11000000000000000
2FhPage 1ch1_iod_div[6]ch1_iod_div[5]ch1_iod_div[4]ch1_iod_div[3]ch1_iod_div[2]ch1_iod_div[1]ch1_iod_div[0]000000000
30hPage 100ch1_outbuf_ctrl[2]ch1_outbuf_ctrl[1]ch1_outbuf_ctrl[0]ch1_mux[1]ch1_mux[0]ch1_iod_mux[1]ch1_iod_mux[0]ch1_iod_div[13]ch1_iod_div[12]ch1_iod_div[11]ch1_iod_div[10]ch1_iod_div[9]ch1_iod_div[8]ch1_iod_div[7]
31hPage 10010100ch1_glitchless_ench1_sync_delay[4]ch1_sync_delay[3]ch1_sync_delay[2]ch1_sync_delay[1]ch1_sync_delay[0]ch1_sync_ench1_mute_selch1_mute
32hPage 100000000000000ch1_1p8vdet0
33hPage 1ch2_iod_div[4]ch2_iod_div[3]ch2_iod_div[2]ch2_iod_div[1]ch2_iod_div[0]00000000010
34hPage 1ch2_outbuf_ctrl[2]ch2_outbuf_ctrl[1]ch2_outbuf_ctrl[0]ch2_mux[1]ch2_mux[0]ch2_iod_mux[1]ch2_iod_mux[0]ch2_iod_div[13]ch2_iod_div[12]ch2_iod_div[11]ch2_iod_div[10]ch2_iod_div[9]ch2_iod_div[8]ch2_iod_div[7]ch2_iod_div[6]ch2_iod_div[5]
35hPage 110100ch2_glitchless_ench2_sync_delay[4]ch2_sync_delay[3]ch2_sync_delay[2]ch2_sync_delay[1]ch2_sync_delay[0]ch2_sync_ench2_mute_selch2_mutech2_cmos_pol[1]ch2_cmos_pol[0]
36hPage 1000000000000ch2_1p8vdet000
37hPage 1ch3_iod_div[2]ch3_iod_div[1]ch3_iod_div[0]0000000001000
38hPage 1ch3_outbuf_ctrl[0]ch3_mux[1]ch3_mux[0]ch3_iod_mux[1]ch3_iod_mux[0]ch3_iod_div[13]ch3_iod_div[12]ch3_iod_div[11]ch3_iod_div[10]ch3_iod_div[9]ch3_iod_div[8]ch3_iod_div[7]ch3_iod_div[6]ch3_iod_div[5]ch3_iod_div[4]ch3_iod_div[3]
39hPage 1000ch3_glitchless_ench3_sync_delay[4]ch3_sync_delay[3]ch3_sync_delay[2]ch3_sync_delay[1]ch3_sync_delay[0]ch3_sync_ench3_mute_selch3_mutech3_cmos_pol[1]ch3_cmos_pol[0]ch3_outbuf_ctrl[2]ch3_outbuf_ctrl[1]
3AhPage 10000000000ch3_1p8vdet10011
3BhPage 1ch4_iod_div[0]000000000100000
3ChPage 1ch4_mux[0]ch4_iod_mux[1]ch4_iod_mux[0]ch4_iod_div[13]ch4_iod_div[12]ch4_iod_div[11]ch4_iod_div[10]ch4_iod_div[9]ch4_iod_div[8]ch4_iod_div[7]ch4_iod_div[6]ch4_iod_div[5]ch4_iod_div[4]ch4_iod_div[3]ch4_iod_div[2]ch4_iod_div[1]
3DhPage 10ch4_glitchless_ench4_sync_delay[4]ch4_sync_delay[3]ch4_sync_delay[2]ch4_sync_delay[1]ch4_sync_delay[0]ch4_sync_ench4_mute_selch4_mute00ch4_outbuf_ctrl[2]ch4_outbuf_ctrl[1]ch4_outbuf_ctrl[0]ch4_mux[1]
3EhPage 10011pll_en_cpch0_lvcmos_drv[1]ch0_lvcmos_drv[0]1ch4_1p8vdet1001010
3FhPage 11100100101100100
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