米6体育平台手机版

ZHCSGV7F July 2017 – January 2024 CDCI6214

PRODUCTION DATA

6.12 Closed-Loop Output Jitter Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A = –40°C to 85°C

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
t_{RJ_CL}	RMS phase jitter	int. Range from 10 kHz to 20 MHz , XIN = Crystal 25 MHz, Integer Output Divider, Yx = 156.25 MHz LVDS	500	750	fs
		int. Range from 10 kHz to 20 MHz , XIN = Crystal 25 MHz, Integer Output Divider, Yx = 100 MHz HCSL	386	800	fs
		PCIe Gen 3/4 Common Clock transfer functions applied, XIN = Crystal 25 MHz, Integer Output Divider, Yx = 100 MHz HCSL		500	fs