米6体育平台手机版

ZHCSGV7F July 2017 – January 2024 CDCI6214

PRODUCTION DATA

6.19 Output Synchronization Characteristics

VDDVCO, VDDO12, VDDO34, VDDREF = 1.8 V ±5%, 2.5 V ±5%, 3.3 V ±5% and T_A = –40°C to 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_{SU_SYNC}	Setup time SYNC pulse	With respect to PLL reference rising edge at 100 MHz with R = 1	3			ns
t_{H_SYNC}	Hold time SYNC pulse	With respect to PLL reference rising edge at 100 MHz with R = 1			3	ns
t_{PWH_SYNC}	High pulse width for SYNC	With R = 1, at least 2 PFD periods + 24 feedback pre-scaler periods	60			ns
t_{PWL_SYNC}	Low pulse width for SYNC	With R = 1, at least 1 PFD period	6			ns
t_EN	Individual output enable time⁽¹⁾	Tri-state to first rising edge, f_Y[4:1] < 200 MHz		4		nCK
t_DIS	Individual output disable time⁽¹⁾	Last falling edge to tri-state, f_Y[4:1] < 200 MHz		4		nCK

(1) Output clock cycles of respective output channel. Global output enable handled by digital logic, additional propagation will be added.