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ZHCSGV7F July 2017 – January 2024 CDCI6214

PRODUCTION DATA

10.1 CDCI6214 Registers

Table 10-1 lists the memory-mapped registers for the CDCI6214.

Note:

All register offset addresses not listed in Table 10-1 should be considered as reserved locations and the register contents should not be modified.

Note:

All bit-field combinations not listed in the description column should be considered as reserved combinations and should only be programmed using the given values.

Table 10-1 CDCI6214 Registers

ADDRESS	ACRONYM	REGISTER NAME	SECTION
0h	GENERIC0	Generic setting, device operation mode, synchronization, control pins, reset, and power down.	Go
1h	GENERIC1	Generic settings, GPIO input signal selection.	Go
2h	GENERIC2	Generic settings, GPIO output signal selection.	Go
3h	GENERIC3	Generic settings, EEPROM and frequency increment / decrement.	Go
4h	POWER0	Power-down bits, output channels.	Go
5h	POWER1	Power-down bits, phase-locked-loop.	Go
6h	STATUS0	Status information, calibration bus.	Go
7h	STATUS1	Status information, PLL lock and EEPROM.	Go
8h	STATUS2	Status information, miscellaneous	Go
9h	STATUS3	Status information, live CRC of EEPROM	Go
Ah	EEPROM0	EEPROM, stored CRC of EEPROM	Go
Bh	EEPROM1	EEPROM, direct access read address	Go
Ch	EEPROM2	EEPROM, direct access read data	Go
Dh	EEPROM3	EEPROM, direct access write address	Go
Eh	EEPROM4	EEPROM, direct access write data	Go
Fh	STARTUP0	Start-up configuration, EEPROM lock, auto-calibration, and I2C glitch filter	Go
10h	STARTUP1	Start-up configuration, digital state machine counters	Go
11h	STARTUP2	Start-up configuration, digital state machine counters	Go
18h	REV0	Revision ID	Go
1Ah	INPUT0	Input reference, buffer configuration, and crystal oscillator controls.	Go
1Bh	INPUT1	Input reference, reference divider, and bypass buffers.	Go
1Ch	INPUT_DBG0	Input reference debug, status pin buffers.	Go
1Dh	PLL0	PLL, feedback dividers.	Go
1Eh	PLL1	PLL, charge pump current and clock distribution pre-scaler dividers.	Go
1Fh	PLL2	PLL, loop filter configuration	Go
21h	PLL4	PLL, lock detector and PFD delay	Go
23h	CH1_CTRL0	Output channel 1, RESERVED	Go
24h	CH1_CTRL1	Output channel 1, RESERVED	Go
25h	CH1_CTRL2	Output channel 1, integer divider and mux control.	Go
26h	CH1_CTRL3	Output channel 1, synchronization, digital delay, output buffer, mux and mute controls.	Go
27h	CH1_CTRL4	Output channel 1, divider glitchless enable and spread spectrum controls.	Go
28h	CH1_CTRL5	Output channel 1, RESERVED	Go
29h	CH2_CTRL0	Output channel 2, RESERVED	Go
2Ah	CH2_CTRL1	Output channel 2, RESERVED	Go
2Bh	CH2_CTRL2	Output channel 2, integer divider and mux control.	Go
2Ch	CH2_CTRL3	Output channel 2, synchronization, digital delay, output buffer, mux and mute controls.	Go
2Dh	CH2_CTRL4	Output channel 2, divider glitchless enable and spread spectrum controls.	Go
2Eh	CH2_CTRL5	Output channel 2 , RESERVED	Go
2Fh	CH3_CTRL0	Output channel 3, RESERVED	Go
30h	CH3_CTRL1	Output channel 3, RESERVED	Go
31h	CH3_CTRL2	Output channel 3, integer divider and mux control.	Go
32h	CH3_CTRL3	Output channel 3, synchronization, digital delay, output buffer, mux and mute controls.	Go
33h	CH3_CTRL4	Output channel 3, divider glitchless enable and spread spectrum controls.	Go
34h	CH3_CTRL5	Output channel 3, RESERVED	Go
35h	CH4_CTRL0	Output channel 4, RESERVED	Go
36h	CH4_CTRL1	Output channel 4, RESERVED	Go
37h	CH4_CTRL2	Output channel 4, integer divider and mux control.	Go
38h	CH4_CTRL3	Output channel 4, synchronization, digital delay, output buffer, mux and mute controls.	Go
39h	CH4_CTRL4	Output channel 4, divider glitchless enable and spread spectrum controls.	Go
3Ah	CH4_CTRL5	Output channel 4, RESERVED	Go
3Bh	CHX_CTRL0	Output channels, generic clock distribution and bypass output controls.	Go
3Ch	CHX_CTRL1	Output channels, RESERVED	Go
3Dh	CHX_CTRL2	Output channels, RESERVED	Go
3Eh	CHX_CTRL3	Output channels, RESERVED	Go
3Fh	CHX_CTRL4	Output channels, RESERVED	Go

Complex bit access types are encoded to fit into small table cells. Table 10-2 shows the codes that are used for access types in this section.

Table 10-2 CDCI6214 Access Type Codes

ACCESS TYPE	CODE	DESCRIPTION
READ TYPE
R	R	Read
RC	C R	to Clear Read
WRITE TYPE
W	W	Write
WEX	W	Write
WMC	W	Write
WPD	W	Write
WSC	W	Write
WST	W	Write
RESET OR DEFAULT VALUE
-n		Value after reset or the default value

10.1.1 GENERIC0 Register (Address = 0h) [reset = 0h]

GENERIC0 is shown in Figure 10-1 and described in Table 10-3.

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Figure 10-1 GENERIC0 Register

15	14	13	12	11	10	9	8
i2c_a0	gpio0_input_sel	gpio4_dir_sel	gpio1_dir_sel	gpio0_dir_sel	zdm_clocksel	RESERVED	zdm_mode
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	pll_rst_lockdet	sync	recal	resetn_soft	swrst	powerdown	mode
R/W-0h	R/W-0h	R/WSC-0h	R/WSC-0h	R/W-0h	R/WSC-0h	R/WPD-0h	R/W-0h

Table 10-3 GENERIC0 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15	i2c_a0	R/W	0h	When regcommit is used to program an EEPROM page, using regcommit_page, this defines the LSB of the I²C target address. When a configuration is loaded into the registers from an EEPROM page, this represents the saved LSB bit.
14	gpio0_input_sel	R/W	0h	Input signal select for GPIO0, Pin 8. 0h = RESETN 1h = SYNC
13	gpio4_dir_sel	R/W	0h	GPIO4 direction select. 0h = Input 1h = Output
12	gpio1_dir_sel	R/W	0h	GPIO1 direction select. 0h = Input 1h = Output
11	gpio0_dir_sel	R/W	0h	Direction select for Pin 8. 0h = Input 1h = Output
10	zdm_clocksel	R/W	0h	Selects the internal or external clock for calibration, in the ZDM mode. In non-ZDM mode, always internal clock will be selected and this register doesn't have any meaning. 0h = Internal Feedback 1h = External Feedback
9	RESERVED	R/W	0h	RESERVED
8	zdm_mode	R/W	0h	Zero Delay Mode 0h = ZDM Off 1h = ZDM On
7	RESERVED	R/W	0h	RESERVED.
6	pll_rst_lockdet	R/W	0h	Reset (active high) to PLL lock detect circuit.
5	sync	R/WSC	0h	Generates sync pulse (for output decoder). This is a self clearing register bit and writing '1' will create the SYNC pulse.
4	recal	R/WSC	0h	Self clearing bit. Writing '1' will do the re-calibration. For example - after the configuration followed by calibration if '1' is written to this register the calibration engine will start with the current capcode and cross code.
3	resetn_soft	R/W	0h	Configure the pin RESETN/SYNC as a soft reset. 0h = Hard Reset (reset state machines and registers) 1h = Soft Reset (state machines only, register content stays as is)
2	swrst	R/WSC	0h	Soft reset bit. This is a self clearing bit. Writing a '0' has no effect and writing a '1' creates a reset pulse which resets the digital logic except the programmable registers. Also, this soft reset has similar effect on digital logic as hard reset (RESENTN/SYNC). Soft reset will restart the configuration and calibration.
1	powerdown	R/WPD	0h	Analog Power Down. 0h = Active 1h = Power down
0	mode	R/W	0h	Mode of Operation. 0h = Serial Interface, I2C 1h = Pin Mode, Output Enable

10.1.2 GENERIC1 Register (Address = 1h) [reset = 6A32h]

GENERIC1 is shown in Figure 10-2 and described in Table 10-4.

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Figure 10-2 GENERIC1 Register

15	14	13	12	11	10	9	8
RESERVED						ref_mux_src	ref_mux
R/W-1Ah						R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
gpio4_input_sel				gpio1_input_sel
R/W-3h				R/W-2h

Table 10-4 GENERIC1 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-10	RESERVED	R/W	1Ah	RESERVED
9	ref_mux_src	R/W	0h	Reference mux control signal source. 0h = Pin 1h = ref_mux bit-field
8	ref_mux	R/W	0h	Reference mux bit override. 0h = XIN 1h = REF
7-4	gpio4_input_sel	R/W	3h	GPIO4 input signal select. Do not choose the same signal on gpio1_input_sel. 2h = OE 4h = OE1 5h = OE2 6h = OE3 7h = OE4
3-0	gpio1_input_sel	R/W	2h	GPIO1 input signal select.Do not choose the same signal on gpio4_input_sel. 2h = OE 4h = OE1 5h = OE2 6h = OE3 7h = OE4

10.1.3 GENERIC2 Register (Address = 2h) [reset = 53h]

GENERIC2 is shown in Figure 10-3 and described in Table 10-5.

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Figure 10-3 GENERIC2 Register

15	14	13	12	11	10	9	8
RESERVED	RESERVED	RESERVED		gpio0_output_sel
R/W-0h	R/W-0h	R/W-0h		R/W-0h

7	6	5	4	3	2	1	0
gpio4_output_sel				gpio1_output_sel
R/W-5h				R/W-3h

Table 10-5 GENERIC2 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-12	RESERVED	R/W	0h	Reserved.
11-8	gpio0_output_sel	R/W	0h	GPIO0, Pin 8, output select , 0h = PLL_LOCK 1h = XTAL_OSC 2h = CAL_DONE 3h = CONF_DONE 4h = SYNC_DONE 5h = EEPROM_BUSY 6h = EEPROM_Y12 7h = EEPROM_M12 8h = I2C_LSB 9h = CLK_FSM Ah = CLK_PFD_REF Bh = CLK_PFD_FB Ch = BUF_SYNC Dh = BUF_SCL Eh = BUF_SDA
7-4	gpio4_output_sel	R/W	5h	GPIO4 , output select , 0h = PLL_LOCK 1h = XTAL_OSC 2h = CAL_DONE 3h = CONF_DONE 4h = SYNC_DONE 5h = EEPROM_BUSY 6h = EEPROM_Y12 7h = EEPROM_M12 8h = I2C_LSB 9h = CLK_FSM Ah = CLK_PFD_REF Bh = CLK_PFD_FB Ch = BUF_SYNC Dh = BUF_SCL Eh = BUF_SDA
3-0	gpio1_output_sel	R/W	3h	GPIO1 , output select , 0h = PLL_LOCK 1h = XTAL_OSC 2h = CAL_DONE 3h = CONF_DONE 4h = SYNC_DONE 5h = EEPROM_BUSY 6h = EEPROM_Y12 7h = EEPROM_M12 8h = I2C_LSB 9h = CLK_FSM Ah = CLK_PFD_REF Bh = CLK_PFD_FB Ch = BUF_SYNC Dh = BUF_SCL Eh = BUF_SDA

10.1.4 GENERIC3 Register (Address = 3h) [reset = 0h]

GENERIC3 is shown in Figure 10-4 and described in Table 10-6.

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Figure 10-4 GENERIC3 Register

15	14	13	12	11	10	9	8
disable_crc	update_crc	nvmcommit	regcommit	regcommit_page	RESERVED	RESERVED	RESERVED
R/W-0h	R/WMC-0h	R/WSC-0h	R/WSC-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	RESERVED
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/WSC-0h	R/WSC-0h	R/W-0h

Table 10-6 GENERIC3 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15	disable_crc	R/W	0h	Disable the CRC computation. However if Page is selected CRC will happen after PoR (power on reset from analog). For example- after the calibration if this bit is set to '1' and apply a soft reset (or reset through pin) the configuration will bypass the CRC computation.
14	update_crc	R/WMC	0h	This is a self clearing register bit. Writing a '1' will cause the re-computation of CRC. The computed CRC can be read from the live CRC (nvmlcrc) register after the status bit nvmbusyh = 0.
13	nvmcommit	R/WSC	0h	Commits contents of the EEPROM page selected by REGCOMMIT_PAGE to internal register. This register will self-clear
12	regcommit	R/WSC	0h	Commits contents of the registers to EEPROM selected by REGCOMMIT_PAGE register. This register will self-clear.
11	regcommit_page	R/W	0h	Decide which page of EEPROM to use for the Register/NVM commit operations. Note= this register is used only after the initial power-up configuration from EEPROM if any. Once power-up configuration is done with the page chosen by EEPROMSEL the value of this register will be used for subsequent configurations using Register/NVM commit operations. 0h = Page 0 1h = Page 1
10-3	RESERVED	R/W	0h	Reserved
2-1	RESERVED	R/WSC	0h	Reserved
0	RESERVED	R/W	0h	Reserved

10.1.5 POWER0 Register (Address = 4h) [reset = 54h]

POWER0 is shown in Figure 10-5 and described in Table 10-7.

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Figure 10-5 POWER0 Register

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
pdn_ch4	RESERVED	pdn_ch3	RESERVED	pdn_ch2	RESERVED	pdn_ch1	RESERVED
R/W-0h	R/W-1h	R/W-0h	R/W-1h	R/W-0h	R/W-1h	R/W-0h	R/W-0h

Table 10-7 POWER0 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-8	RESERVED	R/W	0h	Reserved.
7	pdn_ch4	R/W	0h	Powers Down CH4 LDO. 0h = Active 1h = Power down
6	RESERVED	R/W	1h	Reserved.
5	pdn_ch3	R/W	0h	Powers Down CH3 LDO. 0h = Active 1h = Power down
4	RESERVED	R/W	1h	Reserved.
3	pdn_ch2	R/W	0h	Powers Down CH2 LDO. 0h = Active 1h = Power down
2	RESERVED	R/W	1h	Reserved.
1	pdn_ch1	R/W	0h	Powers Down CH1 LDO. 0h = Active 1h = Power down
0	RESERVED	R/W	0h	Reserved.

10.1.6 POWER1 Register (Address = 5h) [reset = 30h]

POWER1 is shown in Figure 10-6 and described in Table 10-8.

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Figure 10-6 POWER1 Register

15	14	13	12	11	10	9	8
RESERVED					pdn_pll_vcobuf2	pdn_pll_vco	pdn_pll_vcobuf
R/W-0h					R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
pdn_pll_cp	pdn_pll_lockdet	pdn_pll_psfbb	pdn_pll_psfba	RESERVED	pdn_pll_pfd	pdn_pll_psfb	pdn_ref
R/W-0h	R/W-0h	R/W-1h	R/W-1h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 10-8 POWER1 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-11	RESERVED	R/W	0h	Reserved.
10	pdn_pll_vcobuf2	R/W	0h	Power down of VCO buffer LDO. 0h = Active 1h = Power down
9	pdn_pll_vco	R/W	0h	Power down of VCO LDO. 0h = Active 1h = Power down
8	pdn_pll_vcobuf	R/W	0h	Power down of VCO buffer. 0h = Active 1h = Power down
7	pdn_pll_cp	R/W	0h	Power down of charge pump LDO. 0h = Active 1h = Power down
6	pdn_pll_lockdet	R/W	0h	Power down of PLL lock detector. 0h = Active 1h = Power down
5	pdn_pll_psfbb	R/W	1h	Power down of PLL feedback pre-scaler. 0h = Active 1h = Power down
4	pdn_pll_psfba	R/W	1h	Active low enable of prescaler-a. Active (low) during PoR and '1' later. 1h = Power Down PFD. 0h = Otherwise.
3	RESERVED	R/W	0h	Reserved.
2	pdn_pll_pfd	R/W	0h	Active low enable of PFD. Inactive (high) till calibration and '0' afterwards. 1h = Power Down PFD. 0h = Otherwise.
1	pdn_pll_psfb	R/W	0h	Active low enable of prescaler. Active (low) during PoR and '1' later. 1h = Powers Down PS, 0h = Otherwise.
0	pdn_ref	R/W	0h	Powers Down Input Path LDO. Kill Switch. Do not use. 1h = PD, 0h = Otherwise.

10.1.7 STATUS0 Register (Address = 6h) [reset = 0h]

STATUS0 is shown in Figure 10-7 and described in Table 10-9.

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Figure 10-7 STATUS0 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
cal_status
R-0h

Table 10-9 STATUS0 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-0	cal_status	R	0h	Calibration word.

10.1.8 STATUS1 Register (Address = 7h) [reset = 0h]

STATUS1 is shown in Figure 10-8 and described in Table 10-10.

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Figure 10-8 STATUS1 Register

15	14	13	12	11	10	9	8
RESERVED				lock_det_a	pll_vco_cal_ready	nvm_rd_error	nvm_wr_error
R-0h				R-0h	R-0h	RC-0h	RC-0h

7	6	5	4	3	2	1	0
rd_error	wr_error	nvmcrcerr	nvmbusy	cal_done	config_done	unlock_s	lock_det
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R/WEX-0h	R-0h

Table 10-10 STATUS1 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-12	RESERVED	R	0h	Reserved.
11	lock_det_a	R	0h	Reads the PLL Lock status. 0h: PLL is Unlocked. 1h: PLL is locked.
10	pll_vco_cal_ready	R	0h	VCO Buffer LDO POR can be read through this register.
9	nvm_rd_error	RC	0h	Occurs when any NVM operation is issued during Read Phase of the NVM. The Read Phase of the NVM includes CRC calculation or a simple read through RD NVM Addr/Data registers from any NVM location or a NVM commit operation.
8	nvm_wr_error	RC	0h	Occurs when any NVM operation is issued during Write Phase of the NVM. Write Phase of the NVM includes a simple write into any NVM location through WR NVM Addr/Data registers or a Register Commit operation.
7	rd_error	R	0h	Reading using the I2C interface with an address above the address of the last register gives this error.
6	wr_error	R	0h	Writing using the I2C interface with an address above the address of the last register gives this error.
5	nvmcrcerr	R	0h	NVM CRC Error Indication. The NVMCRCERR bit is set to 1 if a CRC Error has been detected when reading back from on-chip EEPROM during device configuration. This bit will be cleared when NVMCOMMIT is submitted or Update CRC is issued.
4	nvmbusy	R	0h	NVM Program Busy Indication. The NVMBUSY bit is 1 during an on-chip EEPROM Erase/Program cycle. While NVMBUSY is 1 the on-chip EEPROM cannot be accessed. When the NVM operation is completed this bit will be cleared. NVM related operations are REGcommit NVMcommit CRC calculation or simple Read/Write through RD/WR NVM.
3	cal_done	R	0h	1h = Calibration (Two rounds of Amplitude followed by calibration) is done.
2	config_done	R	0h	1 h = Configuration (CRC Check followed by transfer of EEPROM to registers) is done.
1	unlock_s	R/WEX	0h	Lock Detect Sticky Bit. This indicates the loss of lock of the PLL and this is cleared only by recalibration or a hard reset through RESETN/SYNC pin 0h = locked 1h = unlocked
0	lock_det	R	0h	When the calibration is done frequency may or may not be locked. 1h = Frequency is locked. 0h = Otherwise 0h = unlocked 1h = locked

10.1.9 STATUS2 Register (Address = 8h) [reset = 0h]

STATUS2 is shown in Figure 10-9 and described in Table 10-11.

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Figure 10-9 STATUS2 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
misc_status
R-0h

Table 10-11 STATUS2 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-0	misc_status	R	0h	Miscellaneous status word.

10.1.10 STATUS3 Register (Address = 9h) [reset = 0h]

STATUS3 is shown in Figure 10-10 and described in Table 10-12.

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Figure 10-10 STATUS3 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
nvmlcrc
R-0h

Table 10-12 STATUS3 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-0	nvmlcrc	R	0h	The NVMLCRC register holds the Live CRC byte that has been calculated while reading on-chip EEPROM.

10.1.11 EEPROM0 Register (Address = Ah) [reset = 0h]

EEPROM0 is shown in Figure 10-11 and described in Table 10-13.

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Figure 10-11 EEPROM0 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
nvmscrc
R-0h

Table 10-13 EEPROM0 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-0	nvmscrc	R	0h	Stored CRC value. This value is used to compare with the computed CRC and to update the CRC Status bit

10.1.12 EEPROM1 Register (Address = Bh) [reset = 0h]

EEPROM1 is shown in Figure 10-12 and described in Table 10-14.

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Figure 10-12 EEPROM1 Register

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED		nvm_rd_addr
R/W-0h		R/W-0h

Table 10-14 EEPROM1 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-6	RESERVED	R/W	0h	Reserved.
5-0	nvm_rd_addr	R/W	0h	Writing an address into the NVM WR Address starts the read loop. This register will contain the data read from the EEPROM at the address provided by the NVM WR Address. The address is auto-incremented and subsequent read from the NVM RD Data register will give the data from the next EEPROM location.

10.1.13 EEPROM2 Register (Address = Ch) [reset = 0h]

EEPROM2 is shown in Figure 10-13 and described in Table 10-15.

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Figure 10-13 EEPROM2 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
nvm_rd_data
R-0h

Table 10-15 EEPROM2 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-0	nvm_rd_data	R	0h	Reading from this register will return the data present at the EEPROM from the immediate next address location than what was programmed in the NVM RD Address register since writing into NVM RD Address register already returned the data from EEPROM from the written address. Subsequent read from this register will cause the address to be auto-incremented and cause a read from the next EEPROM location.

10.1.14 EEPROM3 Register (Address = Dh) [reset = 0h]

EEPROM3 is shown in Figure 10-14 and described in Table 10-16.

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Figure 10-14 EEPROM3 Register

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED		nvm_wr_addr
R/W-0h		R/W-0h

Table 10-16 EEPROM3 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-6	RESERVED	R/W	0h	Reserved.
5-0	nvm_wr_addr	R/W	0h	Writing an address into the NVM WR Address starts the write loop. But Writing a data into the NVM WR Data register will program the EEPROM with that data at the address provided by writing into NVM WR Address initially.

10.1.15 EEPROM4 Register (Address = Eh) [reset = 0h]

EEPROM4 is shown in Figure 10-15 and described in Table 10-17.

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Figure 10-15 EEPROM4 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
nvm_wr_data
R/W-0h

Table 10-17 EEPROM4 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-0	nvm_wr_data	R/W	0h	Writing a data into this register will program the EEPROM with the written data at the address given by NVM WR Address. Subsequent write into this register will cause the address to be auto-incremented and cause a program at the next EEPROM location.

10.1.16 STARTUP0 Register (Address = Fh) [reset = 37h]

STARTUP0 is shown in Figure 10-16 and described in Table 10-18.

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Figure 10-16 STARTUP0 Register

15	14	13	12	11	10	9	8
ee_lock				RESERVED			zdm_auto
R/W-0h				R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
bypass_cal	bypass_config	cal_mute	shift_left		gpio3_gf_en	gpio2_gf_en	acal_en
R/W-0h	R/W-0h	R/W-1h	R/W-2h		R/W-1h	R/W-1h	R/W-1h

Table 10-18 STARTUP0 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-12	ee_lock	R/W	0h	Locks EEPROM for regcommit and EEPROM write operations. To unlock, write 5h, any other value to lock.
11-9	RESERVED	R/W	0h	Reserved.
8	zdm_auto	R/W	0h	Setting this bit 1 will allow state machine to control the value of pll_ndiv and pll_psfb internally in Normal/ZDM mode of calibration. If set 0 the user has to manually program the pll_ndiv and pll_psfb
7	bypass_cal	R/W	0h	Bypass the calibration. By default two rounds of calibrations (AC followed by FC) will be done. Setting this bit to 1 will bypass the calibration.
6	bypass_config	R/W	0h	Bypass the configuration. Note that on PoR this bit is zero and hence configuration will happen. However after the first configuration this bit can be set and apply the soft/pin reset so that configuration will be bypassed.
5	cal_mute	R/W	1h	Mute the output during the calibration. 0h = Outputs stay active 1h = Outputs muted
4-3	shift_left	R/W	2h	Divide the ref clock (PFD clock) during calibration by 2 to the power of value 0h = 1 1h = 2 2h = 4 3h = 8
2	gpio3_gf_en	R/W	1h	Enable the glitch filter for SCL, GPIO3. 0h = Disabled 1h = Enabled
1	gpio2_gf_en	R/W	1h	Enable the glitch filter for SDA, GPIO2. 0h = Disabled 1h = Enabled
0	acal_en	R/W	1h	Enable automatic frequency calibration at power-up or EEPROM re-load. 0h = Disabled 1h = Enabled

10.1.17 STARTUP1 Register (Address = 10h) [reset = 921Fh]

STARTUP1 is shown in Figure 10-17 and described in Table 10-19.

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Figure 10-17 STARTUP1 Register

15	14	13	12	11	10	9	8
pll_lock_dly					ac_init_dly
R/W-12h					R/W-10h

7	6	5	4	3	2	1	0
ac_init_dly			cp_dly
R/W-10h			R/W-1Fh

Table 10-19 STARTUP1 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-11	pll_lock_dly	R/W	12h	Wait time before lock detect goes high after the calibration. Expected value is approximately 1 ms. The actual delay will be 4 × T × {programmed value} where T = 200ns typically.
10-5	ac_init_dly	R/W	10h	Peak detector settlig time, that is, pll_en_peakdet_vco going high to first cross code change. Expected value is 1.6 µs. The actual delay will be 4 × T × {programmed value} where T = 200ns typically.
4-0	cp_dly	R/W	1Fh	Delay from vtune driver enable (pll_en_vtune_drv) going high to peak detector enable (pll_en_peakdet_vco) going high. Expected delay is 200 µs. The actual delay will be 64 × T × {programmed value} where T = 200ns typically.

10.1.18 STARTUP2 Register (Address = 11h) [reset = 6C4h]

STARTUP2 is shown in Figure 10-18 and described in Table 10-20.

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Figure 10-18 STARTUP2 Register

15	14	13	12	11	10	9	8
RESERVED	switch_dly				err_cnt
R/W-0h	R/W-0h				R/W-6h

7	6	5	4	3	2	1	0
fc_setl_dly		ac_cmp_dly
R/W-3h		R/W-4h

Table 10-20 STARTUP2 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15	RESERVED	R/W	0h	Reserved.
14-11	switch_dly	R/W	0h	Indicates number of digital clocks to wait before SSM clock is turned off after all the active signals are low. Internally scaled up by 2⁶. Digital clock period is 200ns typically.
10-8	err_cnt	R/W	6h	Indicates how long to wait for before declaring lock detect. In PFD clocks period. 0h = 32 1h = 64 2h = 128 3h = 256
7-6	fc_setl_dly	R/W	3h	Delay between two cap codes in terms of REFCLK period. Expected value is 1 µs. The actual delay will be 32 × T × {programmed value} where T is the refclk period.
5-0	ac_cmp_dly	R/W	4h	Delay between successive cross code change. Expected value is 1 µs. The actual delay will be 4 × T × {programmed value} where T = 200ns typically.

10.1.19 REV0 Register (Address = 18h) [reset = 601h]

REV0 is shown in Figure 10-19 and described in Table 10-21.

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Figure 10-19 REV0 Register

15	14	13	12	11	10	9	8
RESERVED
R/W-6h

7	6	5	4	3	2	1	0
rev_reg
R-1h

Table 10-21 REV0 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-8	Reserved	R	06h	Reserved
7-0	rev_reg	R	1h	Revision ID register. 1h = CDCI6214

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-8

Reserved

06h

Reserved

7-0

rev_reg

Revision ID register.

1h = CDCI6214

10.1.20 INPUT0 Register (Address = 1Ah) [reset = B14h]

INPUT0 is shown in Figure 10-20 and described in Table 10-22.

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Figure 10-20 INPUT0 Register

15	14	13	12	11	10	9	8
ref_inbuf_ctrl	RESERVED	RESERVED	ip_xo_cload
R/W-0h	R/W-0h	R/W-0h	R/W-Bh

7	6	5	4	3	2	1	0
RESERVED		ip_xo_gm				xin_inbuf_ctrl
R/W-0h		R/W-5h				R/W-0h

Table 10-22 INPUT0 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15	ref_inbuf_ctrl	R/W	0h	Reference input buffer select. 0h = LVCMOS 1h = AC-Differential
14	RESERVED	R/W	0h	RESERVED
13	RESERVED	R/W	0h	RESERVED
12-8	ip_xo_cload	R/W	Bh	Selects load cap for XO (up to 9 pF) in 5 bit binary selection). Step size is about 200 fF. 0h = 3.0 pF 1h = 3.2 pF 2h = 3.4 pF 3h = 3.6 pF 4h = 3.8 pF 5h = 4.0 pF 6h = 4.2 pF 7h = 4.4 pF 8h = 4.6 pF 9h = 4.8 pF Ah = 5.0 pF Bh = 5.2 pF Ch = 5.4 pF Dh = 5.6 pF Eh = 5.8 pF Fh = 6.0 pF 10h = 6.2 pF 11h = 6.4 pF 12h = 6.5 pF 13h = 6.7 pF 14h = 6.9 pF 15h = 7.1 pF 16h = 7.3 pF 17h = 7.5 pF 18h = 7.7 pF 19h = 7.9 pF 1Ah = 8.1 pF 1Bh = 8.3 pF 1Ch = 8.5 pF 1Dh = 8.7 pF 1Eh = 8.9 pF 1Fh = 9.0 pF
7-6	RESERVED	R/W	0h	RESERVED
5-2	ip_xo_gm	R/W	5h	Tune bias current for XO. Gm programmability. Typical values: 0h = Disabled 1h = 14 µA 2h = 29 µA 3h = 44 µA 4h = 59 µA 5h = 148 µA 6h = 295 µA 7h = 443 µA 8h = 591 µA 9h = 884 µA Ah = 1177 µA Bh = 1468 µA Ch = 1758 µA
1-0	xin_inbuf_ctrl	R/W	0h	Input buffer select. 0h = XO 1h = CMOS 2h = DIFF

10.1.21 INPUT1 Register (Address = 1Bh) [reset = 0h]

INPUT1 is shown in Figure 10-21 and described in Table 10-23.

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Figure 10-21 INPUT1 Register

15	14	13	12	11	10	9	8
RESERVED	ip_byp_en_ch4	ip_byp_en_ch3	ip_byp_en_ch2	ip_byp_en_ch1	ip_byp_en_y0	ip_byp_mux	ip_rst_rdiv
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
ip_rdiv
R/W-0h

Table 10-23 INPUT1 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15	RESERVED	R/W	0h	RESERVED
14	ip_byp_en_ch4	R/W	0h	Bypass path buffer enable for CH4. This is required to drive a bypass signal using ch4_iod_mux. 0h = disabled 1h = enabled
13	ip_byp_en_ch3	R/W	0h	Bypass path buffer enable for CH3. This is required to drive a bypass signal using ch3_iod_mux. 0h = disabled 1h = enabled
12	ip_byp_en_ch2	R/W	0h	Bypass path buffer enable for CH2. This is required to drive a bypass signal using ch2_iod_mux. 0h = disabled 1h = enabled
11	ip_byp_en_ch1	R/W	0h	Bypass path buffer enable for CH1. This is required to drive a bypass signal using ch1_iod_mux. 0h = disabled 1h = enabled
10	ip_byp_en_y0	R/W	0h	Enable input clock to come out on Y0 buffer.
9	ip_byp_mux	R/W	0h	Selects Y0 clock between "REF_CLK" and "PFD_CLK". 0h = REF 1h = PFD
8	ip_rst_rdiv	R/W	0h	Resets flops in ref divider. Active (high) during power on reset or SWRST or pin reset and inactive afterwards.
7-0	ip_rdiv	R/W	0h	Reference clock divider. 0 = Doubler ON, 1 = /1, 2 = /2. and so forth. 0h = x2 1h = /1 2h = /2 3h = /3 4h = /4 5h = /5 ... FFh = /255

10.1.22 INPUT_DBG0 Register (Address = 1Ch) [reset = 0h]

INPUT_DBG0 is shown in Figure 10-22 and described in Table 10-24.

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Figure 10-22 INPUT_DBG0 Register

15	14	13	12	11	10	9	8
RESERVED		RESERVED		RESERVED			RESERVED
R/W-0h		R/W-0h		R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
RESERVED		RESERVED	RESERVED	RESERVED	RESERVED	RESERVED	RESERVED
R/W-0h		R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 10-24 INPUT_DBG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R/W	0h	RESERVED.
5	RESERVED	R/W	0h	RESERVED
4	RESERVED	R/W	0h	RESERVED
3	RESERVED	R/W	0h	RESERVED
2	RESERVED	R/W	0h	RESERVED
1	RESERVED	R/W	0h	RESERVED
0	RESERVED	R/W	0h	RESERVED

10.1.23 PLL0 Register (Address = 1Dh) [reset = Ch]

PLL0 is shown in Figure 10-23 and described in Table 10-25.

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Figure 10-23 PLL0 Register

15	14	13	12	11	10	9	8
pll_psfb		pll_ndiv
R/W-0h		R/W-Ch

7	6	5	4	3	2	1	0
pll_ndiv
R/W-Ch

Table 10-25 PLL0 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-14	pll_psfb	R/W	0h	Programming bits for PLL feedback pre-scaler. 0h = /4 1h = /5 2h = /6
13-0	pll_ndiv	R/W	Ch	Feedback divider, must be at least 6h.

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

pll_psfb

R/W

Programming bits for PLL feedback pre-scaler.

0h = /4

1h = /5

2h = /6

13-0

pll_ndiv

R/W

Feedback divider, must be at least 6h.

10.1.24 PLL1 Register (Address = 1Eh) [reset = 5140h]

PLL1 is shown in Figure 10-24 and described in Table 10-26.

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Figure 10-24 PLL1 Register

15	14	13	12	11	10	9	8
pll_cp_up						pll_cp_dn
R/W-14h						R/W-14h

7	6	5	4	3	2	1	0
pll_cp_dn				pll_psb		pll_psa
R/W-14h				R/W-0h		R/W-0h

Table 10-26 PLL1 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-10	pll_cp_up	R/W	14h	Programming bits for up current of CP. 0h = 0.0 mA 1h = 0.1 mA 2h = 0.2 mA 3h = 0.3 mA [...] 1Fh = 3.1 mA *37h = 3.2 mA* 38h = 3.3 mA [...] 3Dh = 3.8 mA 3Eh = 3.9 mA 3Fh = 4.0 mA
9-4	pll_cp_dn	R/W	14h	Programming bits for down current of CP. 0h = 0.0 mA 1h = 0.1 mA 2h = 0.2 mA 3h = 0.3 mA [...] 1Fh = 3.1 mA *37h = 3.2 mA* 38h = 3.3 mA [...] 3Dh = 3.8 mA 3Eh = 3.9 mA 3Fh = 4.0 mA
3-2	pll_psb	R/W	0h	Programming bits for pre-scaler B. 0h = /4 1h = /5 2h = /6
1-0	pll_psa	R/W	0h	Programming bits for pre-scaler A. 0h = /4 1h = /5 2h = /6

10.1.25 PLL2 Register (Address = 1Fh) [reset = 1E72h]

PLL2 is shown in Figure 10-25 and described in Table 10-27.

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Figure 10-25 PLL2 Register

15	14	13	12	11	10	9	8
RESERVED		pll_lf_zcap					pll_lf_res
R/W-0h		R/W-Fh					R/W-3h

7	6	5	4	3	2	1	0
pll_lf_res			pll_lf_pcap
R/W-3h			R/W-12h

Table 10-27 PLL2 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-14	RESERVED	R/W	0h	RESERVED.
13-9	pll_lf_zcap	R/W	Fh	Programming bits of cap value of zero of loop-filter. 0h = 000 pF 1h = 030 pF 2h = 060 pF 3h = 090 pF 4h = 120 pF 5h = 150 pF 6h = 180 pF 7h = 210 pF 8h = 240 pF 9h = 270 pF Ah = 300 pF Bh = 330 pF Ch = 360 pF Dh = 390 pF Eh = 420 pF Fh = 450 pF 10h = 480 pF 11h = 510 pF 12h = 540 pF 13h = 570 pF 14h = 600 pF
8-5	pll_lf_res	R/W	3h	Programming bits of res value of zero of loop-filter. 0h = open kΩ 1h = 00.5 kΩ 2h = 01.5 kΩ 3h = 02.5 kΩ 4h = 03.5 kΩ 5h = 04.5 kΩ 6h = 05.5 kΩ 7h = 06.5 kΩ 8h = 07.5 kΩ 9h = 08.5 kΩ Ah = 09.5 kΩ Bh = 10.5 kΩ Ch = 11.5 kΩ
4-0	pll_lf_pcap	R/W	12h	Programming bits of cap value of pole of loop-filter. 0h = 00.0 pF 1h = 00.5 pF 2h = 01.5 pF 3h = 02.5 pF 4h = 03.5 pF 5h = 04.5 pF 6h = 05.5 pF 7h = 06.5 pF 8h = 07.5 pF 9h = 08.5 pF Ah = 09.5 pF Bh = 10.5 pF Ch = 11.5 pF Dh = 12.5 pF Eh = 13.5 pF Fh = 14.5 pF 10h = 15.5 pF 11h = 16.5 pF 12h = 17.5 pF 13h = 18.5 pF 14h = 19.5 pF

10.1.26 PLL4 Register (Address = 21h) [reset = 7h]

PLL4 is shown in Figure 10-26 and described in Table 10-28.

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Figure 10-26 PLL4 Register

15	14	13	12	11	10	9	8
RESERVED	RESERVED			RESERVED			RESERVED
R/W-0h	R/W-0h			R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
RESERVED	pll_pfd_dly_ctrl		pll_lockdet_window			pll_lockdet_wait
R/W-0h	R/W-0h		R/W-1h			R/W-3h

Table 10-28 PLL4 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-7	RESERVED	R/W	0h	Reserved.
6-5	pll_pfd_dly_ctrl	R/W	0h	Programming of PFD reset delay. In PFD period. 0h = 2 1h = 6 2h = 10 3h = 14
4-2	pll_lockdet_window	R/W	1h	Programmability of PFD input and output time window for lock detect. 0h = disabled 1h = typical 1.4 ns 2h = typical 2.6 ns 3h = typical 3.9 ns 4h = typical 5.2 ns 5h = typical 6.4 ns 6h = typical 7.6 ns 7h = typical 8.9 ns
1-0	pll_lockdet_wait	R/W	3h	Programmability of analog lock detect timer. In PFD cycles 0h = 1 1h = 16 2h = 64 3h = 128

10.1.27 CH1_CTRL0 Register (Address = 23h) [reset = 8000h]

CH1_CTRL0 is shown in Figure 10-27 and described in Table 10-29.

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Figure 10-27 CH1_CTRL0 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R/WEX-8000h

Table 10-29 CH1_CTRL0 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-0	RESERVED	R/WEX	8000h	RESERVED

10.1.28 CH1_CTRL1 Register (Address = 24h) [reset = 0h]

CH1_CTRL1 is shown in Figure 10-28 and described in Table 10-30.

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Figure 10-28 CH1_CTRL1 Register

15	14	13	12	11	10	9	8
RESERVED							RESERVED
R/W-0h							R/WEX-0h

7	6	5	4	3	2	1	0
RESERVED
R/WEX-0h

Table 10-30 CH1_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R/W	0h	RESERVED.
8-0	RESERVED	R/WEX	0h	RESERVED.

10.1.29 CH1_CTRL2 Register (Address = 25h) [reset = 8003h]

CH1_CTRL2 is shown in Figure 10-29 and described in Table 10-31.

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Figure 10-29 CH1_CTRL2 Register

15	14	13	12	11	10	9	8
ch1_iod_mux		ch1_iod_div
R/W-2h		R/WEX-3h

7	6	5	4	3	2	1	0
ch1_iod_div
R/WEX-3h

Table 10-31 CH1_CTRL2 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

ch1_iod_mux

R/W

Input Clock selection for IOD.

0h = PSA

1h = PSB

3h = REF

13-0

ch1_iod_div

R/WEX

IOD Division Value. 0h = Powers Down, Output=Input/IOD_DIV

10.1.30 CH1_CTRL3 Register (Address = 26h) [reset = 9h]

CH1_CTRL3 is shown in Figure 10-30 and described in Table 10-32.

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Figure 10-30 CH1_CTRL3 Register

15	14	13	12	11	10	9	8
ch1_sync_delay					ch1_sync_en	RESERVED	ch1_mute_sel
R/W-0h					R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
ch1_mute	ch1_cmos_pol		ch1_outbuf_ctrl			ch1_mux
R/W-0h	R/W-0h		R/W-2h			R/W-1h

Table 10-32 CH1_CTRL3 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-11	ch1_sync_delay	R/W	0h	Sync Delay cycles of IOD Input Clock. One cycle is a period of the selected pre-scaler clock.
10	ch1_sync_en	R/W	0h	Enables SYNC for the channel. 0h = Disabled 1h = Enabled
9	RESERVED	R/W	0h	Reserved.
8	ch1_mute_sel	R/W	0h	Mute selection for Output Channel. 0h = P=L N=H 1h = P=H N=L
7	ch1_mute	R/W	0h	To mute the output on this channel. 0h = Un-mutes the output. 1h = mutes the output.
4-2	ch1_outbuf_ctrl	R/W	2h	Select the output buffer format. 0h = disabled 1h = LVDS ⁽¹⁾ 2h = HCSL 3h = CML 4h = LVPECL
1-0	ch1_mux	R/W	1h	Output Clock Selection. 1h = CH1 2h = CH2

(1) For DC-connection program chx_lvds_cmtrim_inc = 0 and ch[4:1]_1p8vdet in Table 10-53 and Table 10-52 accordingly.

10.1.31 CH1_CTRL4 Register (Address = 27h) [reset = 679h]

CH1_CTRL4 is shown in Figure 10-31 and described in Table 10-33.

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Figure 10-31 CH1_CTRL4 Register

15	14	13	12	11	10	9	8
RESERVED	RESERVED	RESERVED	RESERVED	RESERVED			RESERVED
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-3h			R/W-0h

7	6	5	4	3	2	1	0
RESERVED		RESERVED		RESERVED	RESERVED	RESERVED	ch1_glitchless_en
R/W-1h		R/W-3h		R/W-1h	R/W-0h	R/W-0h	R/W-1h

Table 10-33 CH1_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R/W	0h	RESERVED
11-9	RESERVED	R/W	3h	RESERVED
8	RESERVED	R/W	0h	RESERVED
7-6	RESERVED	R/W	1h	RESERVED
5-4	RESERVED	R/W	3h	RESERVED
3	RESERVED	R/W	1h	RESERVED
2	RESERVED	R/W	0h	RESERVED
1	RESERVED	R/W	0h	RESERVED
0	ch1_glitchless_en	R/W	1h	Enables Glitchless switching for Output Channel. 0h = Immediate 1h = Glitchless

10.1.32 CH1_CTRL5 Register (Address = 28h) [reset = 8h]

CH1_CTRL5 is shown in Figure 10-32 and described in Table 10-34.

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Figure 10-32 CH1_CTRL5 Register

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED				ch1_1p8vdet	RESERVED	RESERVED	RESERVED
R/W-0h				R/W-1h	R/W-0h	R/W-0h	R/W-0h

Table 10-34 CH1_CTRL5 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-4

RESERVED

R/W

RESERVED.

ch1_1p8vdet

R/W

Specify supply on the channel.

0h = 2.5 V or 3.3 V

1h = 1.8 V

2-0

RESERVED

R/W

RESERVED

10.1.33 CH2_CTRL0 Register (Address = 29h) [reset = 8000h]

CH2_CTRL0 is shown in Figure 10-33 and described in Table 10-35.

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Figure 10-33 CH2_CTRL0 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R/WEX-8000h

Table 10-35 CH2_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R/WEX	8000h	RESERVED

10.1.34 CH2_CTRL1 Register (Address = 2Ah) [reset = 0h]

CH2_CTRL1 is shown in Figure 10-34 and described in Table 10-36.

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Figure 10-34 CH2_CTRL1 Register

15	14	13	12	11	10	9	8
RESERVED							RESERVED
R/W-0h							R/WEX-0h

7	6	5	4	3	2	1	0
RESERVED
R/WEX-0h

Table 10-36 CH2_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R/W	0h	RESERVED.
8-0	RESERVED	R/WEX	0h	RESERVED.

10.1.35 CH2_CTRL2 Register (Address = 2Bh) [reset = 0h]

CH2_CTRL2 is shown in Figure 10-35 and described in Table 10-37.

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Figure 10-35 CH2_CTRL2 Register

15	14	13	12	11	10	9	8
ch2_iod_mux		ch2_iod_div
R/W-0h		R/WEX-0h

7	6	5	4	3	2	1	0
ch2_iod_div
R/WEX-0h

Table 10-37 CH2_CTRL2 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

ch2_iod_mux

R/W

Input Clock selection for IOD.

0h = PSA

1h = PSB

3h = REF

13-0

ch2_iod_div

R/WEX

IOD Division Value. 0h = Powers Down, Output = Input/IOD_DIV

10.1.36 CH2_CTRL3 Register (Address = 2Ch) [reset = 8h]

CH2_CTRL3 is shown in Figure 10-36 and described in Table 10-38.

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Figure 10-36 CH2_CTRL3 Register

15	14	13	12	11	10	9	8
ch2_sync_delay					ch2_sync_en	RESERVED	ch2_mute_sel
R/W-0h					R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
ch2_mute	ch2_cmos_pol		ch2_outbuf_ctrl			ch2_mux
R/W-0h	R/W-0h		R/W-2h			R/W-0h

Table 10-38 CH2_CTRL3 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-11	ch2_sync_delay	R/W	0h	Sync Delay cycles of IOD Input Clock. One cycle is a period of the selected pre-scaler clock.
10	ch2_sync_en	R/W	0h	Enables SYNC for the channel. 0h = Disabled 1h = Enabled
9	RESERVED	R/W	0h	RESERVED.
8	ch2_mute_sel	R/W	0h	Mute selection for Output Channel. 0h = P=L N=H 1h = P=H N=L
7	ch2_mute	R/W	0h	To mute the output on this channel. 0h = Un-mutes the output. 1h = mutes the output.
6-5	ch2_cmos_pol	R/W	0h	programmability of output CMOS buffer polarity. 0h = P+ N+ 1h = P+ N– 2h = P– N+ 3h = P– N–
4-2	ch2_outbuf_ctrl	R/W	2h	Select the output buffer format. 0h = disabled 1h = LVDS⁽¹⁾ 2h = HCSL 3h = CML 4h = LVPECL 5h = CMOSPN 6h = CMOSP 7h = CMOSN
1-0	ch2_mux	R/W	0h	Output Clock Selection. 0h = CH1 1h = CH2 2h = CH3

(1) For DC-connection program chx_lvds_cmtrim_inc = 0 and ch[4:1]_1p8vdet in Table 10-53 and Table 10-52 accordingly.

10.1.37 CH2_CTRL4 Register (Address = 2Dh) [reset = 71h]

CH2_CTRL4 is shown in Figure 10-37 and described in Table 10-39.

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Figure 10-37 CH2_CTRL4 Register

15	14	13	12	11	10	9	8
RESERVED	RESERVED	RESERVED	RESERVED	RESERVED			RESERVED
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
RESERVED		RESERVED		RESERVED	RESERVED	RESERVED	ch2_glitchless_en
R/W-1h		R/W-3h		R/W-0h	R/W-0h	R/W-0h	R/W-1h

Table 10-39 CH2_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R/W	0h	RESERVED
11-8	RESERVED	R/W	0h	RESERVED
7-6	RESERVED	R/W	1h	RESERVED
5-4	RESERVED	R/W	3h	RESERVED
3-1	RESERVED	R/W	0h	RESERVED
0	ch2_glitchless_en	R/W	1h	Enables Glitchless switching for Output Channel. 0h = Immediate 1h = Glitchless

10.1.38 CH2_CTRL5 Register (Address = 2Eh) [reset = 8h]

CH2_CTRL5 is shown in Figure 10-38 and described in Table 10-40.

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Figure 10-38 CH2_CTRL5 Register

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED				ch2_1p8vdet	RESERVED	RESERVED	RESERVED
R/W-0h				R/W-1h	R/W-0h	R/W-0h	R/W-0h

Table 10-40 CH2_CTRL5 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-4

RESERVED

R/W

RESERVED.

ch2_1p8vdet

R/W

Specify supply on the channel.

0h = 2.5 V or 3.3 V

1h = 1.8 V

2-0

RESERVED

R/W

RESERVED

10.1.39 CH3_CTRL0 Register (Address = 2Fh) [reset = 8000h]

CH3_CTRL0 is shown in Figure 10-39 and described in Table 10-41.

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Figure 10-39 CH3_CTRL0 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R/WEX-8000h

Table 10-41 CH3_CTRL0 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-0	RESERVED	R/WEX	8000h	RESERVED

10.1.40 CH3_CTRL1 Register (Address = 30h) [reset = 0h]

CH3_CTRL1 is shown in Figure 10-40 and described in Table 10-42.

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Figure 10-40 CH3_CTRL1 Register

15	14	13	12	11	10	9	8
RESERVED							RESERVED
R/W-0h							R/WEX-0h

7	6	5	4	3	2	1	0
RESERVED
R/WEX-0h

Table 10-42 CH3_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R/W	0h	RESERVED.
8-0	RESERVED	R/WEX	0h	RESERVED

10.1.41 CH3_CTRL2 Register (Address = 31h) [reset = 0h]

CH3_CTRL2 is shown in Figure 10-41 and described in Table 10-43.

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Figure 10-41 CH3_CTRL2 Register

15	14	13	12	11	10	9	8
ch3_iod_mux		ch3_iod_div
R/W-0h		R/WEX-0h

7	6	5	4	3	2	1	0
ch3_iod_div
R/WEX-0h

Table 10-43 CH3_CTRL2 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

ch3_iod_mux

R/W

Input Clock selection for IOD.

0h = PSA

1h = PSB

3h = REF

13-0

ch3_iod_div

R/WEX

IOD Division Value. 0h = Powers Down, Output=Input/IOD_DIV

10.1.42 CH3_CTRL3 Register (Address = 32h) [reset = 4h]

CH3_CTRL3 is shown in Figure 10-42 and described in Table 10-44.

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Figure 10-42 CH3_CTRL3 Register

15	14	13	12	11	10	9	8
ch3_sync_delay					ch3_sync_en	RESERVED	ch3_mute_sel
R/W-0h					R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
ch3_mute	ch3_cmos_pol		ch3_outbuf_ctrl			ch3_mux
R/W-0h	R/W-0h		R/W-1h			R/W-0h

Table 10-44 CH3_CTRL3 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-11	ch3_sync_delay	R/W	0h	Sync Delay cycles of IOD Input Clock. One cycle is a period of the selected pre-scaler clock.
10	ch3_sync_en	R/W	0h	Enables SYNC for the channel. 0h = Disabled 1h = Enabled
9	RESERVED	R/W	0h	RESERVED.
8	ch3_mute_sel	R/W	0h	Mute selection for Output Channel. 0h = P=L N=H 1h = P=H N=L
7	ch3_mute	R/W	0h	To mute the output on this channel. 0h = Un-mutes the output. 1h = mutes the output.
6-5	ch3_cmos_pol	R/W	0h	programmability of output CMOS buffer polarity. 0h = P+ N+ 1h = P+ N– 2h = P– N+ 3h = P– N–
4-2	ch3_outbuf_ctrl	R/W	1h	Select the output buffer format. 0h = disabled 1h = LVDS⁽¹⁾ 2h = HCSL 3h = CML 4h = LVPECL 5h = CMOSPN 6h = CMOSP 7h = CMOSN
1-0	ch3_mux	R/W	0h	Output Clock Selection. 0h = CH2 1h = CH3 2h = CH4

(1) For DC-connection program chx_lvds_cmtrim_inc = 0 and ch[4:1]_1p8vdet in Table 10-53 and Table 10-52 accordingly.

10.1.43 CH3_CTRL4 Register (Address = 33h) [reset = 671h]

CH3_CTRL4 is shown in Figure 10-43 and described in Table 10-45.

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Figure 10-43 CH3_CTRL4 Register

15	14	13	12	11	10	9	8
RESERVED	RESERVED	RESERVED	RESERVED	RESERVED			RESERVED
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-3h			R/W-0h

7	6	5	4	3	2	1	0
RESERVED		RESERVED		RESERVED	RESERVED	RESERVED	ch3_glitchless_en
R/W-1h		R/W-3h		R/W-0h	R/W-0h	R/W-0h	R/W-1h

Table 10-45 CH3_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R/W	0h	RESERVED
11-9	RESERVED	R/W	3h	RESERVED
8	RESERVED	R/W	0h	RESERVED
7-6	RESERVED	R/W	1h	RESERVED
5-4	RESERVED	R/W	3h	RESERVED
3-1	RESERVED	R/W	0h	RESERVED
0	ch3_glitchless_en	R/W	1h	Enables Glitchless switching for Output Channel. 0h = Immediate 1h = Glitchless

10.1.44 CH3_CTRL5 Register (Address = 34h) [reset = 8h]

CH3_CTRL5 is shown in Figure 10-44 and described in Table 10-46.

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Figure 10-44 CH3_CTRL5 Register

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED				ch3_1p8vdet	RESERVED	RESERVED	RESERVED
R/W-0h				R/W-1h	R/W-0h	R/W-0h	R/W-0h

Table 10-46 CH3_CTRL5 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-4

RESERVED

R/W

RESERVED.

ch3_1p8vdet

R/W

Specify supply on the channel.

0h = 2.5 V or 3.3 V

1h = 1.8 V

2-0

RESERVED

R/W

RESERVED

10.1.45 CH4_CTRL0 Register (Address = 35h) [reset = 8000h]

CH4_CTRL0 is shown in Figure 10-45 and described in Table 10-47.

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Figure 10-45 CH4_CTRL0 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R/WEX-8000h

Table 10-47 CH4_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R/WEX	8000h	RESERVED

10.1.46 CH4_CTRL1 Register (Address = 36h) [reset = 0h]

CH4_CTRL1 is shown in Figure 10-46 and described in Table 10-48.

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Figure 10-46 CH4_CTRL1 Register

15	14	13	12	11	10	9	8
RESERVED							RESERVED
R/W-0h							R/WEX-0h

7	6	5	4	3	2	1	0
RESERVED
R/WEX-0h

Table 10-48 CH4_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R/W	0h	RESERVED.
8-0	RESERVED	R/WEX	0h	RESERVED

10.1.47 CH4_CTRL2 Register (Address = 37h) [reset = 0h]

CH4_CTRL2 is shown in Figure 10-47 and described in Table 10-49.

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Figure 10-47 CH4_CTRL2 Register

15	14	13	12	11	10	9	8
ch4_iod_mux		ch4_iod_div
R/W-0h		R/WEX-0h

7	6	5	4	3	2	1	0
ch4_iod_div
R/WEX-0h

Table 10-49 CH4_CTRL2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

ch4_iod_mux

R/W

Input Clock selection for IOD.

0h = PSA

1h = PSB

3h = REF

13-0

ch4_iod_div

R/WEX

IOD Division Value. 0h = Powers Down, Output=Input/IOD_DIV.

10.1.48 CH4_CTRL3 Register (Address = 38h) [reset = 4h]

CH4_CTRL3 is shown in Figure 10-48 and described in Table 10-50.

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Figure 10-48 CH4_CTRL3 Register

15	14	13	12	11	10	9	8
ch4_sync_delay					ch4_sync_en	RESERVED	ch4_mute_sel
R/W-0h					R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
ch4_mute	ch4_cmos_pol		ch4_outbuf_ctrl			ch4_mux
R/W-0h	R/W-0h		R/W-1h			R/W-0h

Table 10-50 CH4_CTRL3 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-11	ch4_sync_delay	R/W	0h	Sync Delay cycles of IOD Input Clock. One cycle is a period of the selected pre-scaler clock.
10	ch4_sync_en	R/W	0h	Enables SYNC for the channel. 0h = Disabled 1h = Enabled
9	RESERVED	R/W	0h	RESERVED.
8	ch4_mute_sel	R/W	0h	Mute selection for Output Channel. 0h = P=L N=H 1h = P=H N=L
7	ch4_mute	R/W	0h	To mute the output on this channel. 0h = Un-mutes the output. 1h = mutes the output.
4-2	ch4_outbuf_ctrl	R/W	1h	Select the output buffer format. 0h = disabled 1h = LVDS⁽¹⁾ 2h = HCSL 3h = CML 4h = LVPECL
1-0	ch4_mux	R/W	0h	Output Clock Selection. 0h = Previous Channel, 1h = Current Channel, 2h = Next Channel, 3h = AGND 0h = CH3 1h = CH4

(1) For DC-connection program chx_lvds_cmtrim_inc = 0 and ch[4:1]_1p8vdet in Table 10-53 and Table 10-52 accordingly.

10.1.49 CH4_CTRL4 Register (Address = 39h) [reset = 71h]

CH4_CTRL4 is shown in Figure 10-49 and described in Table 10-51.

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Figure 10-49 CH4_CTRL4 Register

15	14	13	12	11	10	9	8
RESERVED	RESERVED	RESERVED	RESERVED	RESERVED			RESERVED
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
RESERVED		RESERVED		RESERVED	RESERVED	RESERVED	ch4_glitchless_en
R/W-1h		R/W-3h		R/W-0h	R/W-0h	R/W-0h	R/W-1h

Table 10-51 CH4_CTRL4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R/W	0h	RESERVED
11-8	RESERVED	R/W	0h	RESERVED
7-6	RESERVED	R/W	1h	RESERVED
5-4	RESERVED	R/W	3h	RESERVED
3-1	RESERVED	R/W	0h	RESERVED
0	ch4_glitchless_en	R/W	1h	Enables Glitchless switching for Output Channel. 0h = Immediate 1h = Glitchless

10.1.50 CH4_CTRL5 Register (Address = 3Ah) [reset = 8h]

CH4_CTRL5 is shown in Figure 10-50 and described in Table 10-52.

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Figure 10-50 CH4_CTRL5 Register

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED				ch4_1p8vdet	RESERVED	RESERVED	RESERVED
R/W-0h				R/W-1h	R/W-0h	R/W-0h	R/W-0h

Table 10-52 CH4_CTRL5 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-4

RESERVED

R/W

RESERVED.

ch4_1p8vdet

R/W

Specify supply on the channel.

0h = 2.5 V or 3.3 V

1h = 1.8 V

2-0

RESERVED

R/W

RESERVED

10.1.51 CHX_CTRL0 Register (Address = 3Bh) [reset = 61h]

CHX_CTRL0 is shown in Figure 10-51 and described in Table 10-53.

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Figure 10-51 CHX_CTRL0 Register

15	14	13	12	11	10	9	8
RESERVED	RESERVED	chx_rst	chx_lvds_cmtrim_inc		chx_lvds_cmtrim_dec		chx_diffbuf_ibias_trim
R/W-0h	R/W-0h	R/W-0h	R/W-0h		R/W-0h		R/W-3h

7	6	5	4	3	2	1	0
chx_diffbuf_ibias_trim			chx_lvcmos_drv	RESERVED	ch0_lvcmos_drv		RESERVED
R/W-3h			R/W-1h	R/W-0h	R/W-0h		R/W-1h

Table 10-53 CHX_CTRL0 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-14	RESERVED	R/W	0h	RESERVED
13	chx_rst	R/W	0h	All Channel RST during power up and later. 1h = RST, 0h = Normal.
12-11	chx_lvds_cmtrim_inc	R/W	0h	Increments differential output buffer output common-mode programmability. Use either CHX_LVDS_CMTRIM_INC or CHX_LVDS_CMTRIM_DEC.
10-9	chx_lvds_cmtrim_dec	R/W	0h	Decrements differential output buffer output common-mode programmability. Increment Use either CHX_LVDS_CMTRIM_INC or CHX_LVDS_CMTRIM_DEC.
8-5	chx_diffbuf_ibias_trim	R/W	3h	Differential output buffer tail current programmability. Ch = 350 µA 8h = 400 µA 4h = 450 µA 0h = 500 µA 0h = 500 µA 1h = 550 µA 2h = 600 µA 3h = 650 µA
4	chx_lvcmos_drv	R/W	1h	Adjust CH1 to CH4 LVCMOS driver strength. 0h = Normal 1h = Fast
3	RESERVED	R/W	1h	RESERVED
2-1	ch0_lvcmos_drv	R/W	0h	Enable Y0 channel and adjust LVCMOS driver strength. 0h = Off 1h = Normal 3h = Fast
0	RESERVED	R/W	1h	RESERVED

10.1.52 CHX_CTRL1 Register (Address = 3Ch) [reset = 18h]

CHX_CTRL1 is shown in Figure 10-52 and described in Table 10-54.

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Figure 10-52 CHX_CTRL1 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R/W-18h

Table 10-54 CHX_CTRL1 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-0	RESERVED	R/W	18h	RESERVED

10.1.53 CHX_CTRL2 Register (Address = 3Dh) [reset = 1500h]

CHX_CTRL2 is shown in Figure 10-53 and described in Table 10-55.

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Figure 10-53 CHX_CTRL2 Register

15	14	13	12	11	10	9	8
RESERVED		RESERVED	RESERVED
R/W-0h		R/W-0h	R/W-15h

7	6	5	4	3	2	1	0
RESERVED	RESERVED	RESERVED	RESERVED	RESERVED
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 10-55 CHX_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R/W	0h	RESERVED
12-8	RESERVED	R/W	15h	RESERVED
7-0	RESERVED	R/W	0h	RESERVED

10.1.54 CHX_CTRL3 Register (Address = 3Eh) [reset = 4210h]

CHX_CTRL3 is shown in Figure 10-54 and described in Table 10-56.

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Figure 10-54 CHX_CTRL3 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R/W-4210h

Table 10-56 CHX_CTRL3 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-0	RESERVED	R/W	4210h	RESERVED

10.1.55 CHX_CTRL4 Register (Address = 3Fh) [reset = 210h]

CHX_CTRL4 is shown in Figure 10-55 and described in Table 10-57.

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Figure 10-55 CHX_CTRL4 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R/W-210h

Table 10-57 CHX_CTRL4 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-0	RESERVED	R/W	210h	RESERVED

10.1.56 DBG0 Register (Address = 42h) [reset = 200h]

DBG0 is shown in Figure 10-56 and described in Table 10-58.

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Figure 10-56 DBG0 Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R/W-200h

Table 10-58 DBG0 Register Field Descriptions

BIT	FIELD	TYPE	RESET	DESCRIPTION
15-0	RESERVED	R/W	200h	RESERVED