9.2.2.7 Dead Time Setting Guidelines

For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor is important for preventing shoot-through during dynamic switching.

The UCC21520-Q1 dead time specification in the electrical table is defined as the time interval from 90% of one channel’s falling edge to 10% of the other channel’s rising edge (see

Figure 30). This definition ensures that the dead time setting is independent of the load condition, and guarantees linearity through manufacture testing. However, this dead time setting may not reflect the dead time in the power converter system, since the dead time setting is dependent on the external gate drive turn-on/off resistor, DC-Link switching voltage/current, as well as the input capacitance of the load transistor.

Here is a suggestion on how to select an appropriate dead time for UCC21520-Q1:

Equation 22.

where

• DT_setting: UCC21520-Q1 dead time setting in ns, DT_Setting = 10 × RDT(in kΩ).
• DT_Req: System required dead time between the real V_GS signal of the top and bottom switch with enough margin, or ZVS requirement.
• T_{F_Sys}: In-system gate turn-off falling time at worst case of load, voltage/current conditions.
• T_{R_Sys}: In-system gate turn-on rising time at worst case of load, voltage/current conditions.
• T_D(on): Turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold.

In the example, DT_Setting is set to 250 ns.

It should be noted that the UCC21520-Q1 dead time setting is decided by the DT pin configuration (See Programmable Dead Time (DT) Pin), and it cannot automatically fine-tune the dead time based on system conditions. It is recommended to parallel a ceramic capacitor, 2.2 nF or above, close to the DT pin with R_DT to achieve better noise immunity.