11.1 Layout Guidelines

One must pay close attention to PCB layout in order to achieve optimum performance for the UCC21520-Q1. Below are some key points.

Component Placement:

• Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins and between the VDD and VSS pins to support high peak currents when turning on the external power transistor.
• To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the source of the top transistor and the source of the bottom transistor must be minimized.
• It is recommended to place the dead-time setting resistor, R_DT, and its bypassing capacitor close to DT pin of the UCC21520-Q1.
• It is recommended to bypass using a ≈1nF low ESR/ESL capacitor, C_DIS, close to DIS pin when connecting to a µC with distance.

Grounding Considerations:

• It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the transistors. The gate driver must be placed as close as possible to the transistors.
• Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and area on the circuit board is important for ensuring reliable operation.

High-Voltage Considerations:

• To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination that may compromise the UCC21520-Q1’s isolation performance.
• For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could operate with a DC-link voltage up to 1500 V_DC, one should try to increase the creepage distance of the PCB layout between the high and low-side PCB traces.

Thermal Considerations:

• A large amount of power may be dissipated by the UCC21520-Q1 if the driving voltage is high, the load is heavy, or the switching frequency is high (refer to Estimate Gate Driver Power Loss for more details). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal impedance (θ_JB).
• Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority on maximizing the connection to VSSA and VSSB (see Figure 45 and Figure 46). However, high voltage PCB considerations mentioned above must be maintained.
• If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and VSSB pins to internal ground or power planes through multiple vias of adequate size. However, keep in mind that there shouldn’t be any traces/coppers from different high voltage planes overlapping.