ZHCSGZ9G October   2017  – November 2022 TUSB564

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-Level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 USB3.1 Modes
      6. 8.4.6 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
      6. 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
      7. 8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
      8. 8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Support for DisplayPort UFP_D Pin Assignment E
      4. 9.2.4 PCB Insertion Loss Curves
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RNQ Package 40-Pin (WQFN) Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
DP0p 40 Diff O DP Differential positive output for DisplayPort Lane 0.
DP0n 39 Diff O DP Differential negative output for DisplayPort Lane 0.
DP1p 37 Diff O DP Differential positive output for DisplayPort Lane 1.
DP1n 36 Diff O DP Differential negative output for DisplayPort Lane 1.
DP2p 34 Diff O DP Differential positive output for DisplayPort Lane 2.
DP2n 33 Diff O DP Differential negative output for DisplayPort Lane 2.
DP3p 31 Diff O DP Differential positive output for DisplayPort Lane 3.
DP3n 30 Diff O DP Differential negative output for DisplayPort Lane 3.
TX1n 10 Diff I/O Differential negative input for DisplayPort or differential negative output for USB3.1 upstream facing port.
TX1p 9 Diff I/O Differential positive input for DisplayPort or differential positive output for USB3.1 upstream facing port.
RX1n 13 Diff I Differential negative input for DisplayPort or USB3.1 upstream facing port.
RX1p 12 Diff I Differential positive input for DisplayPort or USB 3.1 upstream facing port.
RX2p 16 Diff I Differential positive input for DisplayPort or USB 3.1 upstream facing port.
RX2n 15 Diff I Differential negative input for DisplayPort or USB 3.1 upstream facing port.
TX2p 19 Diff I/O Differential positive input for DisplayPort or differential positive output for USB3.1 upstream Facing port.
TX2n 18 Diff I/O Differential negative input for DisplayPort or differential negative output for USB3.1 upstream Facing port.
SSTXp 8 Diff I Differential positive input for USB3.1 downstream facing port.
SSTXn 7 Diff I Differential negative input for USB3.1 downstream facing port.
SSRXp 5 Diff O Differential positive output for USB3.1 downstream facing port.
SSRXn 4 Diff O Differential negative output for USB3.1 downstream facing port.
EQ1 14 4 Level I This pin along with EQ0 sets the USB receiver equalizer gain for upstream facing RX1 and RX2 when USB used. Up to 11dB of EQ available.
EQ0 11 4 Level I This pin along with EQ1 sets the USB receiver equalizer gain for upstream facing RX1 and RX2 when USB used. Up to 11 dB of EQ available.
EN 29 2 Level I
(PD)		 Device Enable, when I2C_EN = '0'. Device disable function not used when I2C_EN ≠ '0'.
L = Device Disabled
H = Device Enabled
On rising edge of EN pin, the device will sample all 4-level inputs including the I2C_EN pin. EN pin will not reset the I2C registers.
HPDIN 32 2 Level I Hot Plug Detect. This pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is Low for greater than 2ms, all DisplayPort lanes are disabled while the AUX to SBU switch will remain closed.
I2C_EN 17 4 Level I I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0'.
0 = GPIO mode (I2C disabled)
R = TI Test Mode (I2C enabled at 3.3 V)
F = I2C enabled at 1.8 V
1 = I2C enabled at 3.3 V.
SBU1 24 I/O, CMOS SBU1. This pin should be DC coupled to the SBU1 pin on the Type-C receptacle. A 2-M ohm resistor to GND is also recommended.
SBU2 25 I/O, CMOS SBU2. This pin should be DC coupled to the SBU2 pin on the Type-C receptacle. A 2-M ohm resistor to GND is also recommended.
AUXp 26 I/O, CMOS AUXp. DisplayPort AUX positive I/O connected to the DisplayPort sink through a AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 1M resistor to DP_PWR (3.3 V). This pin along with AUXN is used by the TUSB564 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C.
AUXn 27 I/O, CMOS AUXn. DisplayPort AUX negative I/O connected to the DisplayPort sink through a AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 1M resistor to GND. This pin along with AUXP is used by the TUSB564 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C.
DPEQ1 2 4 Level I DisplayPort Receiver EQ. This along with DPEQ0 will select the DisplayPort receiver equalization gain.
DPEQ0/A1 35 4 Level I DisplayPort Receiver EQ. This along with DPEQ1 will select the DisplayPort receiver equalization gain. When I2C_EN ≠ '0', this pin will also set the TUSB564 I2C address.
SSEQ1 3 4 Level I Along with SSEQ0, sets the USB receiver equalizer gain for downstream facing SSTXP/N.
SSEQ0/A0 38 4 Level I Along with SSEQ1, sets the USB receiver equalizer gain for downstream facing SSTXP/N. When I2C_EN ≠ '0', this pin will also set the TUSB564 I2C address. If I2C_EN = “F”, then this pin must be set to “F” or “0”.
FLIP/SCL 21 2 Level I
(Failsafe)
(PD)		 When I2C_EN = ’0’ this is Flip control pin, otherwise this pin is I2C clock. . When used for I2C clock pullup to I2C controller's VCC I2C supply.
CTL0/SDA 22 2 Level I
(Failsafe)
(PD)		 When I2C_EN = '0' this is a USB3.1 Switch control pin, otherwise this pin is I2C data. When used for I2C data pullup to I2C controller's VCC I2C supply.
CTL1 23 2 Level I
(Failsafe)
(PD)		 DP Alt mode Switch Control Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort functionality. Otherwise, when I2C_EN ≠ '0', DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled.
H = DisplayPort Enabled.
VCC 6, 20, 28 P 3.3-V Power Supply
NC 1 NC No connect pin. Leave open.
GND Thermal Pad G Ground
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