6.5.1 External Peripheral Interface (EPI)
The EPI provides access to external devices using a parallel path. Unlike communications peripherals such as SSI, UART, and I2C, the EPI acts as a bus to external peripherals and memory.
The EPI has the following features:
- 8-, 16-, or 32-bit dedicated parallel bus for external peripherals and memory
- Memory interface supports contiguous memory access independent of data bus width, thus enabling code execution directly from SDRAM, SRAM, and flash memory
- Blocking and nonblocking reads
- Separates processor from timing details through use of an internal write FIFO
- Efficient transfers using µDMA
- Separate channels for read and write
- Read channel request asserted by programmable levels on the internal Nonblocking Read FIFO (NBRFIFO)
- Write channel request asserted by empty on the internal Write FIFO (WFIFO)
The EPI supports three primary functional modes: SDRAM mode, traditional host-bus mode, and general-purpose mode. The EPI module also provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same way as a communication mechanism and is speed-controlled using clocking.
- SDRAM mode
- Supports ×16 (single data rate) SDRAM at up to 60 MHz
- Supports low-cost SDRAMs up to 64MB (512 Mb)
- Includes automatic refresh and access to all banks and rows
- Includes a sleep (standby) mode to keep contents active with minimal power draw
- Multiplexed address and data interface for reduced pin count
- Host-bus mode
- Traditional ×8 and ×16 MCU bus interface capabilities
- Similar device compatibility options as PIC, ATmega, 8051, and others
- Access to SRAM, NOR flash memory, and other devices, with up to 1MB of addressing in nonmultiplexed mode and 256MB in multiplexed mode (512MB in host bus 16 mode with no byte selects)
- Support for up to 512Mb PSRAM in quad chip select mode, with dedicated configuration register read and write enable
- Support of both muxed and demuxed address and data
- Access to a range of devices supporting the nonaddress FIFO ×8 and ×16 interface variant, with support for external FIFO (XFIFO) EMPTY and FULL signals
- Speed controlled, with read and write data wait-state counters
- Support for read or write burst mode to Host Bus
- Multiple chip-select modes including single, dual, and quad chip selects, with and without ALE
- External iRDY signal provided for stall capability of reads and writes
- Manual chip-enable (or use extra address pins)
- General-purpose mode
- Wide parallel interfaces for fast communications with CPLDs and FPGAs
- Data widths up to 32 bits
- Data rates up to 150 MB/second
- Optional "address" sizes from 4 bits to 20 bits
- Optional clock output, read and write strobes, framing (with counter-based size), and clock-enable input
- General parallel GPIO
- 1 to 32 bits, FIFO with speed control
- Useful for custom peripherals or for digital data acquisition and actuator controls