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ZHCSH74B december 2017 – august 2023 LMK61E07

PRODUCTION DATA

6.15 PLL Clock Output Jitter Characteristics

VDD = 3.3 V ± 5%, T_A = –40°C to 85°C⁽¹⁾⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
RJ	RMS phase jitter⁽²⁾ (12 kHz – 20 MHz)	f_OUT ≥ 100 MHz, Integer-N PLL, All output types		100	200	fs RMS
RJ	RMS phase jitter⁽²⁾ (12 kHz – 20 MHz)	f_OUT ≥ 100 MHz, Fractional-N PLL, All output types		150	300	fs RMS

(1) Refer to Parameter Measurement Information for relevant test conditions.

(2) Ensured by characterization.

(3) Phase jitter measured with Agilent E5052 signal source analyzer.