米6体育平台手机版

ZHCSHA6E May 2009 – January 2018 ADS1013 , ADS1014 , ADS1015

PRODUCTION DATA.

over operating ambient temperature range and VDD = 2.0 V to 5.5 V (unless otherwise noted)

		FAST MODE		HIGH-SPEED MODE		UNIT
		MIN	MAX	MIN	MAX	UNIT
f_SCL	SCL Clock Frequency	0.01	0.4	0.01	3.4	MHz
t_BUF	Bus free time between START and STOP condition	600		160		ns
t_HDSTA	Hold time after repeated START condition. After this period, the first clock is generated.	600		160		ns
t_SUSTA	Setup time for a repeated START condition	600		160		ns
t_SUSTO	Setup time for STOP condition	600		160		ns
t_HDDAT	Data hold time	0		0		ns
t_SUDAT	Data setup time	100		10		ns
t_LOW	Low period of the SCL clock pin	1300		160		ns
t_HIGH	High period for the SCL clock pin	600		60		ns
t_F	Rise time for both SDA and SCL signals⁽¹⁾		300		160	ns
t_R	Fall time for both SDA and SCL signals⁽¹⁾		300		160	ns

(1) For high-speed mode maximum values, the capacitive load on the bus line must not exceed 400 pF.

Figure 1. I²C Interface Timing