ZHCSHF4J May   2004  – January 2018 TPS51116

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1. 3.1 典型应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Dissipation Ratings
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VDDQ SMPS, Light Load Condition
      2. 7.3.2  Low-Side Driver
      3. 7.3.3  High-Side Driver
      4. 7.3.4  Current Sensing Scheme
      5. 7.3.5  PWM Frequency and Adaptive On-Time Control
      6. 7.3.6  VDDQ Output Voltage Selection
      7. 7.3.7  VTT Linear Regulator and VTTREF
      8. 7.3.8  Controling Outputs Using the S3 and S5 Pins
      9. 7.3.9  Soft-Start Function and Powergood Status
      10. 7.3.10 VDDQ and VTT Discharge Control
      11. 7.3.11 Current Protection for VDDQ
      12. 7.3.12 Current Protection for VTT
      13. 7.3.13 Overvoltage and Undervoltage Protection for VDDQ
      14. 7.3.14 Undervoltage Lockout (UVLO) Protection, V5IN (PWP), V5FILT (RGE)
      15. 7.3.15 Input Capacitor, V5IN (PWP), V5FILT (RGE)
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDDQ SMPS, Dual PWM Operation Modes
      2. 7.4.2 Current Mode Operation
      3. 7.4.3 D-CAP™ Mode Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 DDR3 Application With Current Mode
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Pin Connections
        2. 8.2.2.2 Choose the inductor
        3. 8.2.2.3 Choose rectifying (low-side) MOSFET
        4. 8.2.2.4 Choose output capacitance
        5. 8.2.2.5 Determine f0 and calculate RC
        6. 8.2.2.6 Calculate CC2
        7. 8.2.2.7 Calculate CC.
        8. 8.2.2.8 Determine the value of R1 and R2.
      3. 8.2.3 Application Curves
    3. 8.3 DDR3 Application With D−CAP™ Mode
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Pin Connections
        2. 8.3.2.2 Choose the Components
      3. 8.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

6.6 Electrical Characteristics

over operating free-air temperature range VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IV5IN1 Supply current 1, V5IN(1) TA = 25°C, No load, VS3 = VS5 = 5 V,
COMP connected to capacitor		 0.8 2 mA
IV5IN2 Supply current 2, V5IN(1) TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,
COMP connected to capacitor		 300 600 μA
IV5IN3 Supply current 3, V5IN(1) TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V, VCOMP = 5 V 240 500
IV5INSDN Shutdown current, V5IN(1) TA = 25°C, No load, VS3 = VS5 = 0 V 0.1 1.0
IVLDOIN1 Supply current 1, VLDOIN TA = 25°C, No load, VS3 = VS5 = 5 V 1 10
IVLDOIN2 Supply current 2, VLDOIN TA = 25°C, No load, VS3 = 5 V, VS5 = 0 V, 0.1 10
IVLDOINSDN Standby current, VLDOIN TA = 25°C, No load, VS3 = VS5 = 0 V 0.1 1.0
VTTREF OUTPUT
VVTTREF Output voltage, VTTREF VVDDQSNS/2 V
VVTTREFTOL Output voltage tolerance –10 mA < IVTTREF< 10 mA,
VVDDQSNS = 2.5 V, Tolerance to VVDDQSNS/2		 –20 20 mV
–10 mA < IVTTREF< 10 mA,
VVDDQSNS = 1.8 V, Tolerance to VVDDQSNS/2		 –18 18
–10 mA < IVTTREF< 10 mA,
VVDDQSNS = 1.5 V, Tolerance to VVDDQSNS/2		 –15 15
–10 mA < IVTTREF< 10 mA,
VVDDQSNS = 1.2 V, Tolerance to VVDDQSNS/2		 –12 12
VVTTREFSRC Source current VVDDQSNS = 2.5 V, VVTTREF = 0 V –20 –40 –80 mA
VVTTREFSNK Sink current VVDDQSNS = 2.5 V, VVTTREF = 2.5 V 20 40 80
VDDQ OUTPUT
VVDDQ Output voltage, VDDQ TA = 25°C, VVDDQSET = 0 V, No load 2.465 2.500 2.535 V
0°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load(2) 2.457 2.500 2.543
–40°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load (2) 2.440 2.500 2.550
TA = 25°C, VVDDQSET = 5 V, No load (2) 1.776 1.800 1.824
0°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No load(2) 1.769 1.800 1.831
–40°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No load(2) 1.764 1.800 1.836
–40°C ≤ TA ≤ 85°C, Adjustable mode, No load(2) 0.75 3.0
VVDDQSET VDDQSET regulation voltage TA = 25°C, Adjustable mode 742.5 750.0 757.5 mV
0°C ≤ TA ≤ 85°C, Adjustable mode 740.2 750.0 759.8
–40°C ≤ TA ≤ 85°C, Adjustable mode 738.0 750.0 762.0
RVDDQSNS Input impedance, VDDQSNS VVDDQSET = 0 V 215 kΩ
VVDDQSET = 5 V 180
Adjustable mode 460
IVDDQSET Input current, VDDQSET VVDDQSET = 0.78 V, COMP = Open –0.04 μA
VVDDQSET = 0.78 V, COMP = 5 V –0.06
IVDDQDisch Discharge current, VDDQ VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
VMODE = 0 V		 10 40 mA
IVLDOINDisch Discharge current, VLDOIN VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
VMODE = 0.5 V		 700 mA
VTT OUTPUT
VVTTSNS Output voltage, VTT VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 2.5 V 1.25 V
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.8 V 0.9
VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.5 V 0.75
VVTTTOL25 VTT output voltage tolerance to VTTREF VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, IVTT = 0 A –20 20 mV
VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, |IVTT| < 1.5 A –30 30
VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, |IVTT| < 3 A –40 40
VVTTTOL18 VTT output voltage tolerance to VTTREF VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V, IVTT = 0 A –20 20 mV
VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V, |IVTT| < 1 A –30 30
VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V, |IVTT| < 2 A –40 40
VVTTTOL15 VTT output voltage tolerance to VTTREF VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V, IVTT = 0 A –20 20 mV
VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V, |IVTT| < 1 A –30 30
VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V, |IVTT| < 2 A –40 40
VVTTTOL12 VTT output voltage tolerance to VTTREF VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V, IVTT = 0 A –20 20 mV
VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V, |IVTT| < 1 A –30 30
VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V, |IVTT| < 1.5 A –40 40
IVTTOCLSRC Source current limit, VTT VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.19 V, PGOOD = HI 3.0 3.8 6.0 A
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = 0 V 1.5 2.2 3.0
IVTTOCLSNK Sink current limit, VTT VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.31 V, PGOOD = HI 3.0 3.6 6.0
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVDDQ 1.5 2.2 3.0
IVTTLK Leakage current, VTT VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2 –10 10 μA
IVTTBIAS Input bias current, VTTSNS VS3 = 5 V, VVTTSNS = VVDDQSNS /2 –1 –0.1 1
IVTTSNSLK Leakage current, VTTSNS VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2 –1 1
IVTTDisch Discharge current, VTT TA = 25°C, VS3 = VS5 = VVDDQSNS = 0 V,
VVTT = 0.5 V		 10 17 mA
TRANSCONDUCTANCE AMPLIFIER
gm Gain TA = 25°C 240 300 360 μS
ICOMPSNK COMP maximum sink current VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.7 V, VCOMP = 1.28 V 13 μA
ICOMPSRC COMP maximum source
current		 VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.3 V, VCOMP = 1.28 V –13
VCOMPHI COMP high clamp voltage VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.3 V, VCS = 0 V 1.31 1.34 1.37 V
VCOMPLO COMP low clamp voltage VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.7 V, VCS = 0 V 1.18 1.21 1.24
DUTY CONTROL
tON Operating on-time VIN = 12 V, VVDDQSET = 0 V 520 ns
tON0 Startup on-time VIN = 12 V, VVDDQSNS = 0 V 125
tON(min) Minimum on-time TA = 25°C(2) 100
tOFF(min) Minimum off-time TA = 25°C(2) 350
ZERO CURRENT COMPARATOR
VZC Zero current comparator offset –6 0 6 mV
OUTPUT DRIVERS
RDRVH DRVH resistance Source, IDRVH = –100 mA 3 6 Ω
Sink, IDRVH = 100 mA 0.9 3
RDRVL DRVL resistance Source, IDRVL = –100 mA 3 6
Sink, IDRVL = 100 mA 0.9 3
tD Dead time LL-low to DRVL-on(2) 10 ns
DRVL-off to DRVH-on(2) 20
INTERNAL BST DIODE
VFBST Forward voltage VV5IN-VBST , IF = 10 mA, TA = 25°C 0.7 0.8 0.9 V
IVBSTLK VBST leakage current VVBST = 34 V, VLL = 28 V, VVDDQ = 2.6 V,
TA = 25°C		 0.1 1.0 μA
PROTECTIONS
VOCL Current limit threshold VPGND-CS , PGOOD = HI, VCS< 0.5 V 50 60 70 mV
VPGND-CS , PGOOD = LO, VCS< 0.5 V 20 30 40
ITRIP Current sense sink current TA = 25°C, VCS> 4.5 V, PGOOD = HI 9 10 11 μA
TA = 25°C, VCS> 4.5 V, PGOOD = LO 4 5 6
TCITRIP TRIP current temperature
coefficient		 RDS(on) sense scheme, On the basis
of TA = 25°C(2) 		4500 ppm/°C
VOCL(off) Overcurrent protection COMP offset (VV5IN-CS - VPGND-LL), VV5IN-CS = 60 mV,
VCS> 4.5 V (2) 		–5 0 5 mV
VR(trip) Current limit threshold setting range VV5IN-CS(2)(1) 30 150
POWERGOOD COMPARATOR
VTVDDQPG VDDQ powergood threshold PG in from lower 92.5% 95.0% 97.5%
PG in from higher 102.5% 105.0% 107.5%
PG hysteresis 5%
IPG(max) PGOOD sink current VVTT = 0 V, VPGOOD = 0.5 V 2.5 7.5 mA
tPG(del) PGOOD delay time Delay for PG in 80 130 200 μs
UNDERVOLTAGE LOCKOUT/LOGIC THRESHOLD
VUVV5IN V5IN UVLO threshold
voltage		 Wake up 3.7 4.0 4.3 V
Hysteresis 0.2 0.3 0.4
VTHMODE MODE threshold No discharge 4.7
Non-tracking discharge 0.1
VTHVDDQSET VDDQSET threshold voltage 2.5 V output 0.08 0.15 0.25
1.8 V output 3.5 4.0 4.5
VIH High-level input voltage S3, S5 2.2
VIL Low-level input voltage S3, S5 0.3
VIHYST Hysteresis voltage S3, S5 0.2
VINLEAK Logic input leakage current S3, S5, MODE –1 1 μA
VINVDDQSET Input leakage/ bias current VDDQSET –1 1
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP VDDQ OVP trip threshold voltage OVP detect 110% 115% 120%
Hysteresis 5%
tOVPDEL VDDQ OVP propagation
delay (2) 		1.5 μs
VUVP Output UVP trip threshold UVP detect 70%
Hysteresis 10%
tUVPDEL Output UVP propagation delay(2) 32 cycle
tUVPEN Output UVP enable delay(2) 1007
THERMAL SHUTDOWN
TSDN Thermal SDN threshold (2) Shutdown temperature 160 °C
Hysteresis 10
(1) V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices.
(2) Specified by design. Not production tested.
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