米6体育平台手机版

ZHCSHN9A February 2018 – April 2018 LMK05028

PRODUCTION DATA.

7.5 Electrical Characteristics

Over Recommended Operating Conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Power Supply Characteristics
IDD_IN0, IDD_IN1, IDD_IN3	Core Supply Current (VDD_INx)			3.5	10	mA
IDD_IN2	Core Supply Current (VDD_IN2)			6	14	mA
IDD_XO	Core Supply Current (VDD_XO)			25	33	mA
IDD_TCXO	Core Supply Current (VDD_TCXO)	Configuration A⁽¹⁾		1	4	mA
IDD_TCXO	Core Supply Current (VDD_TCXO)	Configuration B⁽²⁾		6	9	mA
IDD_PLL1	Core Supply Current (VDD_PLL1)	Configuration A⁽¹⁾		160	188	mA
IDD_PLL1	Core Supply Current (VDD_PLL1)	Configuration B⁽²⁾		185	217	mA
IDD_PLL2	Core Supply Current (VDD_PLL2)	Configuration A⁽¹⁾		138	160	mA
IDD_PLL2	Core Supply Current (VDD_PLL2)	Configuration B⁽²⁾		160	187	mA
IDD_DIG	Core Supply Current (VDD_DIG)	Configuration A⁽¹⁾		34	59	mA
IDD_DIG	Core Supply Current (VDD_DIG)	Configuration B⁽²⁾		42	70	mA
IDDO_x	Output Supply Current⁽⁹⁾ (VDDO_x = 3.3 V ± 5%)	AC-LVDS		22	28	mA
		AC-CML		24	32	mA
		AC-LVPECL		27	34	mA
		HCSL		33	42	mA
IDDO_x	Output Supply Current⁽¹⁰⁾ (VDDO_x = 3.3 V ± 5%)	AC-LVDS (x2)		32	40	mA
		AC-CML (x2)		37	45	mA
		AC-LVPECL (x2)		41	51	mA
		HCSL (x2)		55	67	mA
IDD_PDN	Total Supply Current (all VDD and VDDO pins, 3.3 V)	Device powered-down (PDN pin held low)		40		mA
Reference Input Characteristics (INx)
f_IN	Input frequency range⁽³⁾	Differential input⁽⁴⁾	5		750	MHz
f_IN	Input frequency range⁽³⁾	LVCMOS input	1E-6		250	MHz
V_IN-SE	Single-ended input voltage swing	LVCMOS input, DC-coupled to INx_P	1			V
V_IDpp	Differential input voltage swing, peak-peak (\|V_P– V_N\|)⁽¹⁴⁾	Differential input	0.4		2	V
dV/dt	Input slew rate⁽³⁾		0.2			V/ns
I_IN	Input leakage	50-Ω and 100-Ω internal terminations disabled	-350		350	µA
C_IN	Input capacitance	Single-ended, each pin		2		pF
XO Input Characteristics (XO)
f_CLK	Input frequency range⁽³⁾		10		100	MHz
V_IN-SE	Single-ended input voltage swing	LVCMOS input, DC-coupled to XO_P	1		2.6	V
V_IDpp	Differential input voltage swing, peak-peak (\|V_P – V_N\|)⁽¹⁴⁾	Differential input	0.4		2	V
dV/dt	Input slew rate⁽³⁾		0.2			V/ns
IDC	Input duty cycle		40		60	%
I_IN	Input leakage	50-Ω and 100-Ω internal terminations disabled	-350		350	µA
C_IN	Input capacitance	Single-ended, each pin		1		pF
TCXO/OCXO Input Characteristics (TCXO_IN)
f_TCXO	Input frequency⁽³⁾		10		54	MHz
V_IN	Input voltage swing	AC-coupled	0.8		1.3	V
V_BIAS	Input bias voltage	Weak internal bias		0.6		V
dV/dt	Input slew rate⁽³⁾		0.2			V/ns
IDC	Input duty cycle		40		60	%
C_IN	Input capacitance			10		pF
APLL/VCO Charateristics
f_VCO1	VCO1 Frequency range		4.8		5.4	GHz
f_VCO2	VCO2 Frequency range		5.5		6.2	GHz
1.8-V LVCMOS Output Characteristics (OUTx)
f_OUT	Output frequency⁽³⁾		1E-6		200	MHz
V_OH	Output high voltage	I_OH = 1 mA	1.2			V
V_OL	Output low voltage	I_OL = 1 mA			0.4	V
I_OH	Output high current			-23		mA
I_OL	Output low current			24		mA
t_R/t_F	Output rise/fall time⁽³⁾	20% to 80%		250		ps
t_SK	Output-to-output skew⁽³⁾	Same post divider, output divide values, and output type			100	ps
t_SK	Output-to-output skew⁽³⁾	Same post divider, output divide values, LVCMOS-to-DIFF			1.5	ns
PN_FLOOR	Output phase noise floor (f_OFFSET > 10 MHz)	66.66 MHz		-155		dBc/Hz
ODC	Output duty cycle⁽³⁾⁽¹²⁾		45		55	%
R_OUT	Output impedance			50		Ω
2.5-V LVCMOS Output Characteristics (OUTx)
f_OUT	Output frequency⁽³⁾		1E-6		200	MHz
V_OH	Output high voltage	I_OH = 1 mA	1.9			V
V_OL	Output low voltage	I_OL = 1 mA			0.525	V
I_OH	Output high current			-48		mA
I_OL	Output low current			55		mA
t_R/t_F	Output rise/fall time⁽³⁾	20% to 80%		250		ps
t_SK	Output-to-output skew⁽³⁾	Same post divider, output divide values, and output type			100	ps
t_SK	Output-to-output skew⁽³⁾	Same post divider, output divide values, LVCMOS-to-DIFF			1.5	ns
PN_FLOOR	Output phase noise floor (f_OFFSET > 10 MHz)	66.66 MHz		-155		dBc/Hz
ODC	Output duty cycle⁽³⁾⁽¹²⁾		45		55	%
R_OUT	Output impedance			50		Ω
AC-LVDS Output Characteristics (OUTx)
f_OUT	Output frequency⁽³⁾⁽⁵⁾				750	MHz
V_OD	Output voltage swing (V_OH - V_OL)	f_OUT> 25 MHz	250	400	450	mV
V_ODpp	Differential output voltage swing, peak-to-peak			2×V_OD		V
V_OS	Output common mode		100		430	mV
t_SK	Output-to-output skew⁽³⁾	Same post divider, output divide values, and output type			100	ps
t_R/t_F	Output rise/fall time⁽³⁾	20% to 80%, < 300 MHz		225	350	ps
t_R/t_F	Output rise/fall time⁽³⁾	± 100 mV around center point, ≥ 300 MHz		75	150	ps
PN_FLOOR	Output phase noise floor (f_OFFSET > 10 MHz)	156.25 MHz		-160		dBc/Hz
ODC	Output duty cycle⁽³⁾⁽¹²⁾		45		55	%
AC-CML Output Characteristics (OUTx)
f_OUT	Output frequency⁽³⁾⁽⁵⁾				750	MHz
V_OD	Output voltage swing (V_OH - V_OL)		400	600	800	mV
V_ODpp	Differential output voltage swing, peak-to-peak			2×V_OD		V
V_OS	Output common mode		150		550	mV
t_SK	Output-to-output skew⁽³⁾	Same post divider, output divide values, and output type			100	ps
t_R/t_F	Output rise/fall time⁽³⁾	20% to 80%, < 300 MHz		150	300	ps
t_R/t_F	Output rise/fall time⁽³⁾	± 100 mV around center point, ≥ 300 MHz		50	125	ps
PN_FLOOR	Output duty cycle⁽³⁾⁽¹²⁾	156.25 MHz		-160		dBc/Hz
ODC	Output duty cycle⁽³⁾		45		55	%
AC-LVPECL Output Characteristics (OUTx)
f_OUT	Output frequency⁽³⁾⁽⁵⁾				750	MHz
V_OD	Output voltage swing (V_OH - V_OL)		500	850	1000	mV
V_ODpp	Differential output voltage swing, peak-to-peak			2×V_OD		V
V_OS	Output common mode		0.3		0.7	V
t_SK	Output-to-output skew⁽³⁾	Same post divider, output divide values, and output type			100	ps
t_R/t_F	Output rise/fall time⁽³⁾	20% to 80%, < 300 MHz		150	300	ps
t_R/t_F	Output rise/fall time⁽³⁾	± 100 mV around center point, ≥ 300 MHz		25	100	ps
PN_FLOOR	Output phase noise floor (f_OFFSET > 10 MHz)	156.25 MHz		-162		dBc/Hz
ODC	Output duty cycle⁽³⁾⁽¹²⁾		45		55	%
HCSL Output Characteristics (OUTx)
f_OUT	Output frequency⁽³⁾⁽⁵⁾				400	MHz
V_OH	Output high voltage		600		880	mV
V_OL	Output low voltage		-150		150	mV
t_SK	Output-to-output skew⁽³⁾	Same post divider, output divide values, and output type			100	ps
dV/dt	Output slew rate⁽³⁾	Measured from -150 mV to +150 mV on the differential waveform	2.5		6	V/ns
PN_FLOOR	Output phase noise floor (f_OFFSET > 10 MHz)	100 MHz		-158		dBc/Hz
ODC	Output duty cycle⁽³⁾⁽¹²⁾	100 MHz	45		55	%
3-Level Logic Input Characteristics (HW_SW_CTRL, STATUS[1:0])
V_IH	Input high voltage		1.4			V
V_IM	Input mid voltage	Input floating with internal bias and PDN pulled low	0.7		0.9	V
V_IL	Input low voltage				0.4	V
I_IH	Input high current	V_IH = VDD	-40		40	µA
I_IL	Input low current	V_IL = GND	-40		40	µA
C_IN	Input capacitance			2		pF
2-Level Logic Input Characteristics (PDN, GPIO[6:0], SDI, SCK, SCS, INSELx_[1:0])
V_IH	Input high voltage		1.2			V
V_IL	Input low voltage				0.6	V
I_IH	Input high current	V_IH = VDD	-40		40	µA
I_IL	Input low current	V_IL = GND	-40		40	µA
C_IN	Input capacitance			2		pF
Logic Output Characteristics (STATUS[1:0], GPIO[6:5], SDO)
V_OH	Output high voltage	I_OH= 1 mA	1.2			V
V_OL	Output low voltage	I_OL= 1 mA			0.6	V
t_R/t_F	Output rise/fall time	20% to 80%, LVCMOS mode, 1 kΩ to GND		500		ps
SPI Timing Requirements (SDI, SCK, SCS, SDO)
f_SCK	SPI clock rate				20	MHz
t₁	SCS to SCK setup time		10			ns
t₂	SDI to SCK setup time		10			ns
t₃	SDI to SCK hold time		10			ns
t₄	SCK high time		25			ns
t₅	SCK low time		25			ns
t₆	SCK to SDO valid read-back data		10			ns
t₇	SCS pulse width		20			ns
t₈	SDI to SCK hold time		10			ns
I²C Interface Characteristics (SDA, SCL)
V_IH	Input high voltage		1.2			V
V_IL	Input low voltage				0.5	V
I_IH	Input leakage		-15		15	µA
C_IN	Input capacitance			2		pF
V_OL	Output low voltage	I_OL = 3 mA			0.3	V
f_SCL	I²C clock rate	Standard			100	kHz
f_SCL	I²C clock rate	Fast mode			400	kHz
t_SU(START)	START condition setup time	SCL high before SDA low	0.6			µs
t_H(START)	START condition hold time	SCL low after SDA low	0.6			µs
t_W(SCLH)	SCL pulse width high		0.6			µs
t_W(SCLL)	SCL pulse width low		1.3			µs
t_SU(SDA)	SDA setup time		100			ns
t_H(SDA)	SDA hold time	SDA valid after SCL low	0		0.9	µs
t_R(IN)	SDA/SCL input rise time				300	ns
t_F(IN)	SDA/SCL input fall time				300	ns
t_F(OUT)	SDA output fall time	C_BUS ≤ 400 pF			300	ns
t_SU(STOP)	STOP condition setup time		0.6			µs
t_BUS	Bus free time between STOP and START		1.3			µs
Other Characteristics
t_PHO	Input-to-output phase offset	Zero delay mode		2		ns
PSNR	Spur induced by power supply noise (V_N = 50 mVpp)⁽⁶⁾⁽⁷⁾	VDDO_x = 2.5 V or 3.3 V, AC-DIFF or HCSL output		-70		dBc
PSNR	Spur induced by power supply noise (V_N = 50 mVpp)⁽⁶⁾⁽⁷⁾	VDDO_x = 2.5 V, LVCMOS output		-55
PSNR	Spur induced by power supply noise (V_N = 25 mVpp)⁽⁶⁾⁽⁷⁾	VDDO_x = 1.8 V, AC-DIFF or HCSL output		-70
PSNR	Spur induced by power supply noise (V_N = 25 mVpp)⁽⁶⁾⁽⁷⁾	VDDO_x = 1.8 V, LVCMOS output		-45
SPUR	Spur level due to output-to-output crosstalk (adjacent channels)⁽⁷⁾	f_OUTx = 156.25 MHz, f_OUTy = 155.52 MHz, AC-DIFF or HCSL (same output type for both channels)		-75		dBc
PLL Clock Output Performance Characteristics
RJ	RMS phase jitter (12 kHz to 20 MHz)	156.25 MHz AC-DIFF or HCSL output, f_XO = 48.0048 MHz		150	250	fs RMS
PN_TDC	Output close-in phase noise (f_OFFSET = 100 Hz)	122.88 MHz AC-DIFF or HCSL, 3-loop mode, f_XO = 48.0048 MHz, f_TCXO = 10 MHz, f_TCXO-TDC = 20 MHz, BW_REF = 5 Hz, BW_TCXO = 400 Hz		-112		dBc/Hz
BW	DPLL bandwidth range⁽⁸⁾	Programmed bandwidth setting		0.01 to 4000		Hz
J_PK	DPLL closed-loop jitter peaking⁽¹³⁾	f_IN = 25 MHz, f_OUT = 10 MHz, DPLL BW = 0.1 Hz or 10 Hz		0.1		dB
J_TOL	Jitter tolerance	Jitter modulation = 10 Hz, 25.78125 Gbps		6455		UI p-p
t_HITLESS	Phase transient during hitless switch	Valid for a single switchover event between two clock inputs at the same frequency		± 50		ps
f_HITLESS	Frequency transient during hitless switch	Valid for a single switchover event between two clock inputs at the same frequency		± 10		ppb
t_STARTUP	Initial PLL clock start-up time⁽¹¹⁾	From rising edge of PDN to free-running output clocks		20		ms

(1) Configuration A (All blocks on except TCXO_IN and both TCXO-DPLLs): f_IN[0:3] = 25 MHz, f_XO = 48.0048 MHz, TCXO_IN disabled. Both DPLL[1:2] in 2-loop mode, f_VCO1 = 5 GHz, f_VCO2 = 5.5296 GHz, PLL1_P1 = 8, PLL2_P1 = 9.

(2) Configuration B (All blocks on): f_IN[0:3] = 25 MHz, f_XO = 48.0048 MHz, f_TCXO = 10 MHz. Both DPLL[1:2] in 3-loop mode, f_VCO1 = 5 GHz, f_VCO2 = 5.5296 GHz, PLL1_P1 = 8, PLL2_P1 = 9.

(3) Parameter is specified by characterization and is not tested in production.

(4) For a differential input clock below 5 MHz, TI recommends to disable the differential input amplitude monitor and enable at least one other monitor (frequency, window detectors) to validate the input clock. Otherwise, consider using an LVCMOS clock for an input below 5 MHz.

(5) An output frequency over the f_OUT max spec is possible, but the output swing may be less than the V_OD min spec.

(6) PSNR is the single-sideband spur level (in dBc) measured when sinusoidal noise with ampitude V_N and frequency between 100 kHz and 1 MHz is injected onto VDD and VDDO_x pins.

(7) DJ_SPUR (ps pk-pk) = [2 × 10^(dBc/20) / (π × f_OUT) × 1E6], where dBc is the PSNR or SPUR level (in dBc) and f_OUT is the output frequency (in MHz).

(8) Actual loop bandwidth may be lower. Applies to REF-DPLL and TCXO-DPLL. The valid loop bandwidth range may be constrained by the DPLL loop mode and REF-TDC and/or TCXO-TDC frequencies used in a given configuration.

(9) IDDO_x includes supply current for output divider and one output driver with f_OUT = 156.25 MHz or 122.88 MHz.

(10) IDDO_x includes supply current for output divider and two output drivers with f_OUT = 156.25 MHz or 122.88 MHz.

(11) Assumes XO input clock is stable in frequency and amplitude before rising edge of PDN, PLLs start-up using parallel calibration mode, VCO wait timers set to 0.4 ms, PLL wait timers set to 3 ms, and outputs auto-mute during APLL lock only (DPLL auto-mute options disabled).

(12) Parameter is specified for PLL outputs divided from either VCO domain.

(13) The TICS Pro software configures the closed-loop jitter peaking for 0.1 dB or less based on the programmed DPLL bandwidth setting.

(14) Minimum limit applies for the minimum setting of the differential input amplitude monitor.