9.1 Overview

The LMK05028 is a high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications.

The LMK05028 features four reference inputs, two independent PLL channels, and eight output clocks with RMS phase jitter of 150-fs typical. The flexible PLL channels provide programmable loop bandwidths for input jitter and wander attenuation and fractional-N PLL frequency synthesis to generate any output frequency from any input frequency. Each PLL channel has three phase-locked loops comprised of two digital PLLs (DPLLs) and one analog PLL (APLL) with a low-noise integrated VCO. Each channel supports three-loop or two-loop mode configurations to optimize clock performance and solution cost for different use cases.

The reference input muxes support automatic input selection or manual input selection through software or pin control. The reference switchover event will be hitless with superior phase transient performance (50-ps typical). The reference clock input monitoring block monitors the clock inputs and will perform a switchover or holdover when a loss of reference (LOR) is detected. A LOR condition can be detected upon any violation of the threshold limits set for the input monitors, which include amplitude, frequency, missing pulse, runt pulse, and 1-PPS (pulse-per-second) detectors. The threshold limits for each input detector can be set and enabled independently per clock input. The tuning word history monitor feature allows the initial output frequency accuracy upon entry into holdover to be determined by the historical average frequency when locked, minimizing the frequency and phase disturbance during a LOR condition.

The device has eight outputs with programmable drivers, allowing up to eight differential clocks, eight LVCMOS pairs (two outputs per pair), or a combination of both. The output clocks can be selected from either PLL/VCO domain by the output muxes. A 1-PPS output can be supported on outputs 0 and 7. The output dividers have a SYNC feature to allow multiple outputs to be phase-aligned. If needed, zero delay can be enabled to achieve a deterministic phase offset between any specified PLL output clock and its selected input clock.

To support IEEE 1588 PTP slave clock or other clock steering applications, each PLL channel also supports DCO mode with <1-ppt (part per trillion) frequency resolution for precise frequency and phase adjustment through external software or pin control.

The device is fully programmable through I²C or SPI and features custom start-up frequency configuration with the internal EEPROM, which is custom factory pre-programmable and in-system programmable. Internal LDO regulators provide excellent PSNR to reduce the cost and complexity of the power delivery network. The clock input and PLL monitoring status can be observed through the status pins and interrupt registers for full diagnostic capability.