9.2.1 PLL Architecture Overview

Figure 19 shows the 3-loop architecture implemented the same for both PLL channels with exception of the VCO frequency range. Each channel has three phase-locked loops with two digital PLLs (REF-DPLL and TCXO-DPLL) and one analog PLL (APLL) with integrated VCO. The REF-DPLL and TCXO-DPLL are each comprised of a time-to-digital converter (TDC), digital loop filter (DLF), feedback prescaler (PR), and 40-bit fractional feedback (FB) divider with sigma-delta-modulator (SDM or "MASH"). The APLL is comprised of a reference frequency doubler (×2), phase-frequency detector (PFD), loop filter (LF), fractional feedback (N) divider with SDM, and VCO.

1. Fractional divider SDM control node depends on the selected PLL mode configuration.

2. DCO frequency adjustments can be software or pin controlled.

3. PLL cascading options: a) PLL1 VCO1 Loopback to PLL2, b) PLL2 VCO2 Loopback to PLL1.

Figure 19. PLL Architecture (One Channel)

Table 2 summarizes the PLL mode configuration options available in each channel. These modes support a wide range of use cases depending to the clock functionality and performance required in the application. Most applications will use 2-loop REF-DPLL or 3-loop mode for network synchronization clock features such as programmable loop bandwidth for jitter and wander attenuation, hitless switching, precise digital holdover, DCO frequency steering, and/or zero delay mode.

The following sections describe the basic principle of operation for 2-loop and 3-loop modes. See PLL Operating Modes for more details on the PLL modes of operation including holdover.