9.3.9.9 REF-DPLL Reference Divider (R)

The reference clock input paths to each REF-DPLL features a 16-b reference divider (R) for each clock input (IN0 to IN3). The output of each R divider sets the frequencies to the reference input mux and the TDC rate of the REF-DPLL. There are also two additional R dividers for the internal VCO loopback clocks (IN4 and IN5) that could be used in cascaded PLL configurations. IN4 refers to the VCO1 loopback clock to DPLL2 reference input, and IN5 refers to the VCO2 loopback clock to DPLL1 reference input. To support hitless switching between inputs with different frequencies, the R divider can be used to divide the clocks to a single common frequency to the REF-DPLL TDC input.