ZHCSHN9A February   2018  – April 2018 LMK05028

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化方框图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Device Start-Up Modes
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Output Clock Test Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 ITU-T G.8262 (SyncE) Standards Compliance
    2. 9.2 Functional Block Diagrams
      1. 9.2.1 PLL Architecture Overview
      2. 9.2.2 3-Loop Mode
        1. 9.2.2.1 PLL Output Clock Phase Noise Analysis in 3-Loop Mode
      3. 9.2.3 2-Loop REF-DPLL Mode
      4. 9.2.4 2-Loop TCXO-DPLL Mode
      5. 9.2.5 PLL Configurations for Common Applications
    3. 9.3 Feature Description
      1. 9.3.1  Oscillator Input (XO_P/N)
      2. 9.3.2  TCXO/OCXO Input (TCXO_IN)
      3. 9.3.3  Reference Inputs (INx_P/N)
      4. 9.3.4  Clock Input Interfacing and Termination
      5. 9.3.5  Reference Input Mux Selection
        1. 9.3.5.1 Automatic Input Selection
        2. 9.3.5.2 Manual Input Selection
      6. 9.3.6  Hitless Switching
      7. 9.3.7  Gapped Clock Support on Reference Inputs
      8. 9.3.8  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 9.3.8.1 XO Input Monitoring
        2. 9.3.8.2 TCXO Input Monitoring
        3. 9.3.8.3 Reference Input Monitoring
          1. 9.3.8.3.1 Reference Validation Timer
          2. 9.3.8.3.2 Amplitude Monitor
          3. 9.3.8.3.3 Missing Pulse Monitor (Late Detect)
          4. 9.3.8.3.4 Runt Pulse Monitor (Early Detect)
          5. 9.3.8.3.5 Frequency Monitoring
          6. 9.3.8.3.6 Phase Valid Monitor for 1-PPS Inputs
        4. 9.3.8.4 PLL Lock Detectors
        5. 9.3.8.5 Tuning Word History
        6. 9.3.8.6 Status Outputs
        7. 9.3.8.7 Interrupt
      9. 9.3.9  PLL Channels
        1. 9.3.9.1  PLL Frequency Relationships
        2. 9.3.9.2  Analog PLL (APLL)
        3. 9.3.9.3  APLL XO Doubler
        4. 9.3.9.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 9.3.9.5  APLL Loop Filter
        6. 9.3.9.6  APLL Voltage Controlled Oscillator (VCO)
          1. 9.3.9.6.1 VCO Calibration
        7. 9.3.9.7  APLL VCO Post-Dividers (P1, P2)
        8. 9.3.9.8  APLL Fractional N Divider (N) With SDM
        9. 9.3.9.9  REF-DPLL Reference Divider (R)
        10. 9.3.9.10 TCXO/OCXO Input Doubler and M Divider
        11. 9.3.9.11 TCXO Mux
        12. 9.3.9.12 REF-DPLL and TCXO-DPLL Time-to-Digital Converter (TDC)
        13. 9.3.9.13 REF-DPLL and TCXO-DPLL Loop Filter
        14. 9.3.9.14 REF-DPLL and TCXO-DPLL Feedback Dividers
      10. 9.3.10 Output Clock Distribution
      11. 9.3.11 Output Channel Muxes
        1. 9.3.11.1 TCXO/Ref Bypass Mux
      12. 9.3.12 Output Dividers
      13. 9.3.13 Clock Outputs (OUTx_P/N)
        1. 9.3.13.1 AC-Differential Output (AC-DIFF)
        2. 9.3.13.2 HCSL Output
        3. 9.3.13.3 LVCMOS Output (1.8 V, 2.5 V)
        4. 9.3.13.4 Output Auto-Mute During LOL or LOS
      14. 9.3.14 Glitchless Output Clock Start-Up
      15. 9.3.15 Clock Output Interfacing and Termination
      16. 9.3.16 Output Synchronization (SYNC)
      17. 9.3.17 Zero-Delay Mode (ZDM) Configuration
      18. 9.3.18 PLL Cascading With Internal VCO Loopback
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Start-Up Modes
        1. 9.4.1.1 EEPROM Mode
        2. 9.4.1.2 ROM Mode
      2. 9.4.2 PLL Operating Modes
        1. 9.4.2.1 Free-Run Mode
        2. 9.4.2.2 Lock Acquisition
        3. 9.4.2.3 Locked Mode
        4. 9.4.2.4 Holdover Mode
      3. 9.4.3 PLL Start-Up Sequence
      4. 9.4.4 Digitally-Controlled Oscillator (DCO) Mode
        1. 9.4.4.1 DCO Frequency Step Size
        2. 9.4.4.2 DCO Direct-Write Mode
      5. 9.4.5 Zero-Delay Mode (ZDM)
      6. 9.4.6 Cascaded PLL Operation
    5. 9.5 Programming
      1. 9.5.1 Interface and Control
      2. 9.5.2 I2C Serial Interface
        1. 9.5.2.1 I2C Block Register Transfers
      3. 9.5.3 SPI Serial Interface
        1. 9.5.3.1 SPI Block Register Transfer
      4. 9.5.4 Register Map Generation
      5. 9.5.5 General Register Programming Sequence
      6. 9.5.6 EEPROM Programming Flow
        1. 9.5.6.1 EEPROM Programming Using Register Commit (Method #1)
          1. 9.5.6.1.1 Write SRAM Using Register Commit
          2. 9.5.6.1.2 Program EEPROM
        2. 9.5.6.2 EEPROM Programming Using Direct SRAM Writes (Method #2)
          1. 9.5.6.2.1 Write SRAM Using Direct Writes
      7. 9.5.7 Read SRAM
      8. 9.5.8 Read EEPROM
      9. 9.5.9 EEPROM Start-Up Mode Default Configuration
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Device Start-Up Sequence
      2. 10.1.2 Power Down (PDN) Pin
      3. 10.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 10.1.3.1 Mixing Supplies
        2. 10.1.3.2 Power-On Reset (POR) Circuit
        3. 10.1.3.3 Powering Up From a Single-Supply Rail
        4. 10.1.3.4 Power Up From Split-Supply Rails
        5. 10.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
      4. 10.1.4 Slow or Delayed XO Start-Up
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Bypassing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Reliability
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 时钟架构
      2. 13.1.2 TICS Pro
    2. 13.2 文档支持
      1. 13.2.1 相关文档
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14机械、封装和可订购信息

6 Pin Configuration and Functions

RGC Package
64-Pin VQFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
POWER
GND PAD G Ground / Thermal Pad.
The exposed pad must be connected to PCB ground for proper electrical and thermal performance. A 7x7 via pattern is recommended to connect the IC ground pad to the PCB ground layers.
VDD_IN0 3 P Core Supply (3.3 V) for Reference Inputs 0 to 3.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_IN1 16 P
VDD_IN2 9 P
VDD_IN3 4 P
VDD_XO 42 P Core Supply (3.3 V) for XO and TCXO Inputs.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_TCXO 19 P
VDD_APLL1 49 P Core Supply (3.3 V) for PLL1, PLL2, and Digital Blocks.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_APLL2 37 P
VDD_DIG 8 P
VDDO_0 21 P Output Supply (1.8, 2.5, or 3.3 V) for Clock Outputs 0 to 7.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDDO_1 25 P
VDDO_23 30 P
VDDO_45 50 P
VDDO_6 59 P
VDDO_7 63 P
CORE BLOCKS
LF1 47 A External Loop Filter Capacitor for APLL1 and APLL2.
Place a nearby 0.1-µF capacitor on each pin.
LF2 39 A
CAP_APLL1 48 A External Bypass Capacitors for APLL1, APLL2, and Digital Blocks.
Place a nearby 10-µF bypass capacitor on each pin.
CAP_APLL2 38 A
CAP_DIG 7 A
INPUT BLOCKS
IN0_P 1 I DPLL Reference Clock Inputs 0 to 3.
Each input pair can accept a differential or single-ended clock signal for synchronizing the DPLLs. Each pair has a programmable input type with internal termination to support AC- or DC-coupled clocks. A single-ended LVCMOS clock can be applied to the P input with the N input pulled down to ground. An unused input pair can be left floating. LVCMOS input mode is recommended for input frequencies from 5 MHz down to 1 Hz (1 PPS or pulse-per-second).
IN0_N 2 I
IN1_P 14 I
IN1_N 15 I
IN2_P 10 I
IN2_N 11 I
IN3_P 5 I
IN3_N 6 I
XO_P 43 I XO Input.
This input pair can accept a differential or single-ended clock signal from a low-jitter local oscillator to lock the APLLs. This input has a programmable input type with internal termination to support AC- or DC-coupled clocks. A single-ended LVCMOS clock (up to 2.5 V) can be applied to the P input with the N input pulled down to ground.
XO_N 44 I
TCXO_IN 18 I TCXO Input.
This input can accept an AC-coupled sinewave, clipped-sinewave, or single-ended clock signal from a stable oscillator (TCXO/OCXO) to lock the TCXO-DPLL if used by a DPLL configuration. The input swing must be less than 1.3 Vpp before AC-coupling to the input pin, which has weak internal biasing of 0.6 V and no internal termination. Leave pin floating if unused.
OUTPUT BLOCKS
OUT0_P 22 O Clock Outputs 0 to 3 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or 1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs should be terminated if active or left floating if disabled through registers.
The OUT[0:3] bank requires at least one clock from the PLL2 domain if enabled. This bank is preferred for PLL2 clocks to minimize output crosstalk.
OUT0_N 23 O
OUT1_P 27 O
OUT1_N 26 O
OUT2_P 31 O
OUT2_N 32 O
OUT3_P 34 O
OUT3_N 33 O
OUT4_P 51 O Clock Outputs 4 to 7 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or 1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs should be terminated if active or left floating if disabled through registers.
The OUT[4:7] bank requires at least one clock from the PLL1 domain. This bank is preferred for PLL1 clocks to minimize output crosstalk.
OUT4_N 52 O
OUT5_P 54 O
OUT5_N 53 O
OUT6_P 57 O
OUT6_N 58 O
OUT7_P 62 O
OUT7_N 61 O
LOGIC CONTROL / STATUS (2)(3)
HW_SW_CTRL 64 I Device Start-Up Mode Select (3-level, 1.8-V compatible).
This input selects the device start-up mode that determines the memory page used to initialize the registers, serial interface, and logic pin functions. The input level is sampled only at device power-on reset (POR).
See Table 1 for start-up mode descriptions and logic pin functions.
PDN 46 I Device Power-Down (active low).
When PDN is pulled low, the device is in hard reset and all blocks including the serial interface are powered down. When PDN is pulled high, the device is started according to device mode selected by HW_SW_CTRL and begins normal operation with all internal circuits reset to their initial state.
SDA/SDI 35 I/O I2C Serial Data I/O (SDA) or SPI Serial Data Input (SDI). See Table 1.
The default 7-bit I2C address is 11000xxb, where the MSB bits (11000b) are initialized from on-chip EEPROM and the LSB bits (xxb) are determined by the logic input pins. When HW_SW_CTRL is 0, the LSBs are determined by the GPIO[2:1] input levels during POR. When HW_SW_CTRL is 1, the LSBs are fixed to 00b.
SCL/SCK 36 I I2C Serial Clock Input (SCL) or SPI Serial Clock Input (SCK). See Table 1.
GPIO0/SYNCN 45 I Multifunction Inputs or Outputs.
See Table 1.
GPIO1/SCS 24 I
GPIO2/SDO 60 I/O
GPIO3/FINC1 40 I
GPIO4/FDEC1 41 I
GPIO5/FINC2 12 I/O
GPIO6/FDEC2 13 I/O
STATUS1 56 I/O Status Outputs [1:0].
Each output has programmable status signal selection, driver type (3.3-V LVCMOS or open-drain), and status polarity. Open-drain requires an external pullup resistor. Leave pin floating if unused.
STATUS0 55 I/O
INSEL0_1 17 I Manual Reference Input Selection for DPLL1.
INSEL0_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused.
INSEL0_0 20 I
INSEL1_1 29 I Manual Reference Input Selection for DPLL2.
INSEL1_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused.
INSEL1_0 28 I
(1) G = Ground, P = Power, I = Input, O = Output, I/O = Input or Output, A = Analog.
(2) Internal resistors: PDN pin has 200-kΩ pullup to VDD. Each HW_SW_CTRL, GPIO, and STATUS pin has a 150-kΩ bias to VIM (approximately 0.8 V) when PDN = 0 or 400-kΩ pulldown when PDN = 1. Each INSEL pin has an 85-kΩ pullup to 1.8 V when PDN = 0 or 400-kΩ pulldown when PDN = 1.
(3) Unless otherwise noted: Logic inputs are 2-level, 1.8-V compatible inputs. Logic outputs are 3.3-V LVCMOS levels.
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