9.3.16 Output Synchronization (SYNC)

Output SYNC can be used to align two or more output clocks to be phase-aligned at a common rising edge by allowing the output dividers to exit reset on the same PLL post-divider clock cycle. Any output dividers selecting the same PLL post-divider can be synchronized together as a SYNC group by triggering a SYNC event through the hardware pin or software bit.

The following requirements must be met establish a SYNC group for two or more output channels:

• Output dividers have their respective sync enabled (CHx_SYNCEN bit = 1).
• Output dividers have their output mux selecting the same PLL primary post-divider (for example, PLL1 P1 or PRI, PLL1 P2 or SEC).
• The PLL post-divider (PRI and/or SEC) must have the applicable sync bank bit(s) enabled for the output divider bank(s). Examples:
  • PLL1_PRI_CH47_SYNC_BANK should be set when output dividers in OUT[4:7] bank will be synced to PLL1 P1 (PRI).
  • PLL1_SEC_CH03_SYNC_BANK should be set when output dividers in OUT[0:3] bank will be synced to PLL1 P1 (SEC).

A SYNC event can be asserted by the hardware GPIO0/SYNCN pin (active low) or the SYNC_SW register bit (active high). When SYNC is asserted, the SYNC-enabled dividers held are reset and clock outputs are muted. The divider reset and output muting is done synchronously, allowing the outputs to finish their final clock cycle (to avoid a short clock period) before the actual SYNC event. When SYNC is deasserted, the outputs will start with their initial clock phases synchronized or aligned. SYNC can also be used to mute any SYNC-enabled outputs to prevent output clocks from being distributed to down-stream devices until they are configured and ready to accept the incoming clock. The SYNC signal is internally qualified or sampled by the internal digital system clock that runs at 10 MHz nominal. The negative pulse applied to the SYNCN input pin should be greater than 200 ns to be captured by the internal digital system clock. SYNC deassertion can take two cycles of the digital clock before the outputs are released.

Output channels with their sync disabled (CHx_SYNCEN bit = 0) will not be affected by a SYNC event and will continue normal output operation as configured. Also, VCO and PLL post-divider clocks do not stop running during the SYNC so they can continue to source any output channels that do not require synchronization. Output dividers with divide-by-1 (divider bypass mode) are not gated during the SYNC event. Also, SYNC should be disabled and is not supported when the output mux is selecting the XO, TCXO, or DPLL reference clocks.

Figure 51 shows an example of the SYNC timing example for a SYNC group. The SYNC group is comprised of OUT0, OUT6, and OUT7 dividers, which are sourced by the PLL1 P1 (primary) post-divider. Notice that the output divider reset and output mute is applied synchronously by waiting until the last output clock in the group goes low (OUT7).

1. The VCO clock and PLL post-divider clock do not stop running during the SYNC.

Figure 51. Output SYNC Group Timing Example