9.3.18 PLL Cascading With Internal VCO Loopback

PLL cascading can be used when the second PLL (either PLL1 or PLL2) must be precisely locked to the frequency of the first PLL. The internal VCO loopback configuration options are implemented identically on both PLL channels, allowing PLL2 to be cascaded after PLL1 or vice versa. The internal VCO loopback clock from the first PLL can drive the REF-DPLL input path or the TCXO-DPLL input path if the TCXO loopback enable control is set. The second PLL can have reference validation enabled to qualify the VCO loopback clock from the first PLL stage to ensure that the second PLL stage has a stable and valid clock input from the first PLL stage before it acquires lock. The VCO loopback clock can be validated based on when the first PLL stage achieves frequency lock and/or phase lock on the REF-DPLL or frequency lock on the TCXO-DPLL. Once the VCO loopback clock is validated based on the enabled criteria, then the second PLL stage can begin to acquire lock. The VCO loopback dividers, loopback mux, and loopback reference validation options are programmable.

In the example shown in Figure 54, PLL2 is cascaded and locked to PLL1's internal VCO1 loopback clock through the two loopback dividers (fixed and programmable) and TCXO loopback muxes. PLL2 operates with a wide loop bandwidth to precisely track the DCO frequency adjustments applied to PLL1. This effectively applies DCO adjustments to both clock domains simultaneously, which would not be possible if both loops were operating in parallel (not cascaded) with separate DCO controls.

Figure 54. PLL Cascading Example With DCO Frequency Steering