9.4.2.3 Locked Mode

Once locked, the PLL output clocks will be frequency and phase locked to its selected DPLL input clock. While the DPLL is locked, the output clocks will not be affected by frequency drift on the XO or TCXO inputs. The REF-DPLL has a programmable frequency lock detector and phase lock detectors to indicate loss of frequency lock (LOFL) and loss of phase lock (LOPL) status flags, which can be observed through the status pins or status bits. Once frequency lock is detected (LOFL → 0), the tuning word history monitor (if enabled) will begin to accumulate history data that is used to determine the initial output frequency accuracy upon entry into holdover mode.