9.4.4 Digitally-Controlled Oscillator (DCO) Mode

To support IEEE 1588 slave clock and other clock steering applications, each PLL channel supports DCO mode to allow precise output clock frequency adjustment of less than 1 ppt/step. DCO mode can be enabled on either REF-DPLL or TCXO-DPLL loop when operating in locked mode.

The DCO frequency step size can be programmed through the frequency deviation or FDEV register (DPLLy_FDEV bits). The FDEV step value is an offset added to or subtracted from the current numerator value of the DPLL's fractional FB divider SDM that determines the DCO frequency offset at the VCO output.

The DCO frequency increment (FINC) or frequency decrement (FDEC) updates can be controlled through software control or pin control. DCO updates through software control are always available through I²C or SPI by writing to the DPLLy_FDEV_REG_UPDATE register bit. Writing a 0 will increment the DCO frequency by the programmed step size, while writing a 1 will decrement it.

The pin control paths to each DCO block must be enabled through registers. Once enabled, a positive pulse on the GPIO3/FINC1 or GPIO4/FDEC1 pin will apply a corresponding DCO update to DPLL1. Similarly, a positive pulse on the GPIO5/FINC2 or GPIO6/FDEC2 pin will apply a corresponding DCO update to DPLL2. The minimum positive pulse width applied to the FINC or FDEC pins should be greater than 100 ns to be captured by the internal sampling clock. The DCO update rate should limited to less than 1 MHz when using pin control.

Figure 58. DCO Mode Control Options