米6体育平台手机版

ZHCSHO1D November 2018 – January 2019 LMG1210

PRODUCTION DATA.

8.2.2.1 Bypass Capacitor

To properly drive the GaN FETs, TI recommends placing high-quality ceramic bypass capacitors as close as possible between the HB to HS and V_DD to V_SS. If using the LDO, the V_DD-V_SS capacitor is required to be at least 0.3 µF at bias for stability. However, a larger capacitor may be required for many applications.

The bootstrap capacitor must be large enough to support charging the high-side FET and supplying the high-side quiescent current when the high-side FET is on. The required capacitance can be calculated as Equation 7:

Equation 7. (0.5 nC + Q_rr + Q_gH + I_HB × t_on)/ΔV = C_BST,min

where

Q_gH is the gate charge of the high-side GaN FET,
I_HB is the quiescent current of the high-side driver,
t_ON is the maximum on time period of the high side,
Q_rr is the reverse recovery of the bootstrap diode,
0.5 nC is the additional charge per cycle removed from the bootstrap due to high side dynamic current,
and ΔV is the acceptable droop on the bootstrap capacitor voltage.

When using larger bootstrap capacitors, TI recommends that the V_DD-V_SS capacitor also be increased to keep the ratio at least 5 to 1. If this is not maintained, the charging of the bootstrap capacitor can pull the V_DD-V_SS rail down sufficiently to cause UVLO conditions and potentially unwanted behavior.